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Joshua Wise's Git repositories - fpgaboy.git/blobdiff - System.v
wire [15:0] addr;
wire [7:0] data;
wire wr, rd;
+
+ wire irq, tmrirq;
+ wire [7:0] jaddr;
GBZ80Core core(
.clk(clk),
.busaddress(addr),
.busdata(data),
.buswr(wr),
- .busrd(rd));
+ .busrd(rd),
+ .irq(irq),
+ .jaddr(jaddr));
ROM rom(
.address(addr),
.wr(wr),
.rd(rd));
- wire irq, tmrirq;
- wire [7:0] jaddr;
Timer tmr(
.clk(clk),
.wr(wr),
wire [7:0] data;
wire wr, rd;
+ wire irq, tmrirq;
+ wire [7:0] jaddr;
+
// wire [7:0] leds;
// wire [7:0] switches;
.busaddress(addr),
.busdata(data),
.buswr(wr),
- .busrd(rd));
+ .busrd(rd),
+ .irq(irq),
+ .jaddr(jaddr));
ROM rom(
.clk(clk),
.rd(rd),
.serial(serio));
- wire irq, tmrirq;
- wire [7:0] jaddr;
Timer tmr(
.clk(clk),
.wr(wr),
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