reg [7:0] imask = 16'hFFFF;
reg [7:0] ihold = 8'b0;
wire [7:0] imasked = ihold & imask;
+
+ reg rdlatch = 0;
+ reg [15:0] addrlatch = 0;
- assign data = rd ?
- (addr == `ADDR_IF) ? ihold :
- (addr == `ADDR_IE) ? imask :
+ assign data = rdlatch ?
+ (addrlatch == `ADDR_IF) ? ihold :
+ (addrlatch == `ADDR_IE) ? imask :
8'bzzzzzzzz :
8'bzzzzzzzz;
imasked[3] ? 8'h58 :
imasked[4] ? 8'h60 : 8'h00;
- always @(negedge clk)
+ always @(posedge clk)
begin
if (wr && (addr == `ADDR_IF || addr == `ADDR_IE)) begin
case(addr)
end
else
ihold <= ihold | iflag;
+ rdlatch <= rd;
+ addrlatch <= addr;
end
endmodule