RETCC that breaks everything. Why?

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 996ec1092c1973a86f85b9ba24e5099ac301f31c..8bc14e9df01a67155742346789f38a6f3bacb76c 100644 (file)
--- a/System.v
+++ b/System.v
@@ -31,9 +31,9 @@ module InternalRAM(
        
        always @(negedge clk)
        begin
-               if (decode)
-               begin
-                       if (wr)
+               if (decode)     // This has to go this way. The only way XST knows how to do
+               begin                           // block ram is chip select, write enable, and always
+                       if (wr)         // reading. "else if rd" does not cut it ...
                                ram[address[12:0]] <= data;
                        odata <= ram[address[12:0]];
                end