Test interrupts. They work!

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 996ec1092c1973a86f85b9ba24e5099ac301f31c..7319ebf6aceb8cc2f7b7f72a3f0877bb93a39aaa 100644 (file)
--- a/System.v
+++ b/System.v
@@ -31,9 +31,9 @@ module InternalRAM(
        
        always @(negedge clk)
        begin
-               if (decode)
-               begin
-                       if (wr)
+               if (decode)     // This has to go this way. The only way XST knows how to do
+               begin                           // block ram is chip select, write enable, and always
+                       if (wr)         // reading. "else if rd" does not cut it ...
                                ram[address[12:0]] <= data;
                        odata <= ram[address[12:0]];
                end
@@ -70,21 +70,24 @@ module CoreTop(
        output wire [3:0] digits,
        output wire [7:0] seven);
        
-       wire clk;
-       //IBUFG ibuf (.O(clk), .I(iclk));
-       
+       wire clk;       
        CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
 
        wire [15:0] addr;       
        wire [7:0] data;
        wire wr, rd;
+       
+       wire irq, tmrirq;
+       wire [7:0] jaddr;
 
        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),
                .busdata(data),
                .buswr(wr),
-               .busrd(rd));
+               .busrd(rd),
+               .irq(irq),
+               .jaddr(jaddr));
        
        ROM rom(
                .address(addr),
@@ -111,7 +114,7 @@ module CoreTop(
                .switches(switches)
                );
 
-       UART nouart (
+       UART nouart (   /* no u */
     .clk(clk), 
     .wr(wr), 
     .rd(rd), 
@@ -126,14 +129,39 @@ module CoreTop(
                .clk(clk),
                .wr(wr),
                .rd(rd));
+
+       Timer tmr(
+               .clk(clk),
+               .wr(wr),
+               .rd(rd),
+               .addr(addr),
+               .data(data),
+               .irq(tmrirq));
+       
+       Interrupt intr(
+               .clk(clk),
+               .rd(rd),
+               .wr(wr),
+               .addr(addr),
+               .data(data),
+               .vblank(0),
+               .lcdc(0),
+               .tovf(tmrirq),
+               .serial(0),
+               .buttons(0),
+               .master(irq),
+               .jaddr(jaddr));
 endmodule
 
 module TestBench();
-       reg clk = 0;
+       reg clk = 1;
        wire [15:0] addr;
        wire [7:0] data;
        wire wr, rd;
        
+       wire irq, tmrirq;
+       wire [7:0] jaddr;
+       
 //     wire [7:0] leds;
 //     wire [7:0] switches;
        
@@ -143,7 +171,9 @@ module TestBench();
                .busaddress(addr),
                .busdata(data),
                .buswr(wr),
-               .busrd(rd));
+               .busrd(rd),
+               .irq(irq),
+               .jaddr(jaddr));
        
        ROM rom(
                .clk(clk),
@@ -168,6 +198,28 @@ module TestBench();
                .rd(rd),
                .serial(serio));
        
+       Timer tmr(
+               .clk(clk),
+               .wr(wr),
+               .rd(rd),
+               .addr(addr),
+               .data(data),
+               .irq(tmrirq));
+       
+       Interrupt intr(
+               .clk(clk),
+               .rd(rd),
+               .wr(wr),
+               .addr(addr),
+               .data(data),
+               .vblank(0),
+               .lcdc(0),
+               .tovf(tmrirq),
+               .serial(0),
+               .buttons(0),
+               .master(irq),
+               .jaddr(jaddr));
+       
 //     Switches sw(
 //             .clk(clk),
 //             .address(addr),