Yay. Fix retcc. Comparing against an x value - great idea, or greatest idea?

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index cd7f4d1cb35861e609888a53b3f1dc70368edbd2..3cd46e3b1cec513536674259e0045391975673d7 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -401,7 +401,7 @@ module GBZ80Core(
                                        end
                                endcase
                        end
-                       `INSN_RET: begin
+                       `INSN_RET,`INSN_RETCC: begin
                                case (cycle)
                                0:      begin
                                                rd <= 1;
@@ -409,8 +409,6 @@ module GBZ80Core(
                                        end
                                1:      begin   // SPECIAL CASE: cycle does NOT increase linearly with ret!
                                                `EXEC_INC_PC;
-                                               if (opcode != `INSN_RETCC)
-                                                       $stop;
                                                case (opcode[4:3])      // cycle 1 is skipped if we are not retcc
                                                `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
                                                `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
@@ -794,7 +792,7 @@ module GBZ80Core(
                        end
                        `INSN_RET,`INSN_RETCC: begin
                                case (cycle)
-                               0:      if (opcode != `INSN_RETCC)
+                               0:      if (opcode[0])  // i.e., not RETCC
                                                cycle <= 1;     // Skip cycle 1; it gets incremented on the next round.
                                1: begin /* Nothing need happen here. */ end
                                2:      registers[`REG_PCL] <= rdata;