+`ifdef EXECUTE
+ `INSN_POP_reg: begin /* POP is 12 cycles! */
+ case (cycle)
+ 0: begin
+ rd <= 1;
+ address <= {registers[`REG_SPH],registers[`REG_SPL]};
+ end
+ 1: begin
+ rd <= 1;
+ address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+ end
+ 2: begin
+ `EXEC_NEWCYCLE;
+ `EXEC_INC_PC;
+ end
+ endcase
+ end
+`endif
+
+`ifdef WRITEBACK
+ `INSN_POP_reg: begin /* POP is 12 cycles! */
+ case (cycle)
+ 0: begin end
+ 1: begin
+ case (opcode[5:4])
+ `INSN_stack_AF: registers[`REG_F] <= rdata;
+ `INSN_stack_BC: registers[`REG_C] <= rdata;
+ `INSN_stack_DE: registers[`REG_E] <= rdata;
+ `INSN_stack_HL: registers[`REG_L] <= rdata;
+ endcase
+ end
+ 2: begin
+ case (opcode[5:4])
+ `INSN_stack_AF: registers[`REG_A] <= rdata;
+ `INSN_stack_BC: registers[`REG_B] <= rdata;
+ `INSN_stack_DE: registers[`REG_D] <= rdata;
+ `INSN_stack_HL: registers[`REG_H] <= rdata;
+ endcase
+ {registers[`REG_SPH],registers[`REG_SPL]} <=
+ {registers[`REG_SPH],registers[`REG_SPL]} + 2;
+ end
+ endcase
+ end
+`endif