Start refactoring instructions.

[fpgaboy.git] / insn_ld_reg_imm16.v

diff --git a/insn_ld_reg_imm16.v b/insn_ld_reg_imm16.v
new file mode 100644 (file)
index 0000000..b9bd84e
--- /dev/null
+++ b/insn_ld_reg_imm16.v
@@ -0,0 +1,40 @@
+`ifdef EXECUTE
+       `INSN_LD_reg_imm16: begin
+               `EXEC_INC_PC;
+               case (cycle)
+               0:      begin
+                               `EXEC_NEXTADDR_PCINC;
+                               rd <= 1;
+                       end
+               1:      begin
+                               `EXEC_NEXTADDR_PCINC;
+                               rd <= 1;
+                       end
+               2:      begin `EXEC_NEWCYCLE; end
+               endcase
+       end
+`endif
+
+`ifdef WRITEBACK
+       `INSN_LD_reg_imm16: begin
+               case (cycle)
+               0:      begin /* */ end
+               1:      begin
+                               case (opcode[5:4])
+                               `INSN_reg16_BC: registers[`REG_C] <= rdata;
+                               `INSN_reg16_DE: registers[`REG_E] <= rdata;
+                               `INSN_reg16_HL: registers[`REG_L] <= rdata;
+                               `INSN_reg16_SP: registers[`REG_SPL] <= rdata;
+                               endcase
+                       end
+               2:      begin
+                               case (opcode[5:4])
+                               `INSN_reg16_BC: registers[`REG_B] <= rdata;
+                               `INSN_reg16_DE: registers[`REG_D] <= rdata;
+                               `INSN_reg16_HL: registers[`REG_H] <= rdata;
+                               `INSN_reg16_SP: registers[`REG_SPH] <= rdata;
+                               endcase
+                       end
+               endcase
+       end
+`endif