Start refactoring instructions.

[fpgaboy.git] / insn_ld_reg_hl.v

diff --git a/insn_ld_reg_hl.v b/insn_ld_reg_hl.v
new file mode 100644 (file)
index 0000000..3fc7862
--- /dev/null
+++ b/insn_ld_reg_hl.v
@@ -0,0 +1,34 @@
+`ifdef EXECUTE
+       `INSN_LD_reg_HL: begin
+               case(cycle)
+               0:      begin
+                               address <= {registers[`REG_H], registers[`REG_L]};
+                               rd <= 1;
+                       end
+               1:      begin
+                               tmp <= rdata;
+                               `EXEC_INC_PC;
+                               `EXEC_NEWCYCLE;
+                       end
+               endcase
+       end
+`endif
+
+`ifdef WRITEBACK
+       `INSN_LD_reg_HL: begin
+               case (cycle)
+               0:      begin end
+               1:      begin
+                               case (opcode[5:3])
+                               `INSN_reg_A:    registers[`REG_A] <= tmp;
+                               `INSN_reg_B:    registers[`REG_B] <= tmp;
+                               `INSN_reg_C:    registers[`REG_C] <= tmp;
+                               `INSN_reg_D:    registers[`REG_D] <= tmp;
+                               `INSN_reg_E:    registers[`REG_E] <= tmp;
+                               `INSN_reg_H:    registers[`REG_H] <= tmp;
+                               `INSN_reg_L:    registers[`REG_L] <= tmp;
+                               endcase
+                       end
+               endcase
+       end
+`endif