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[fpgaboy.git] / core / GBZ80Core.v

diff --git a/core/GBZ80Core.v b/core/GBZ80Core.v
index a79b78a28946c329661f11fcf84e08b97eabb7a0..4a1e25675b4db43a24903c202065b0b32d38cb68 100644 (file)
--- a/core/GBZ80Core.v
+++ b/core/GBZ80Core.v
@@ -150,65 +150,6 @@ module GBZ80Core(
 `include "allinsns.v"
 `undef LOCALWIRES
 
-       wire [7:0] rlc,rrc,rl,rr,sla,sra,swap,srl;
-       wire [3:0] rlcf,rrcf,rlf,rrf,slaf,sraf,swapf,srlf;
-       wire [7:0] alu_res;
-       wire [3:0] f_res;
-
-       assign rlc   = {tmp[6:0],tmp[7]};
-       assign rlcf  = {(tmp == 0 ? 1'b1 : 1'b0)
-                       ,2'b0,
-                       tmp[7]};
-
-       assign rrc   = {tmp[0],tmp[7:1]};
-       assign rrcf  = {(tmp == 0 ? 1'b1 : 1'b0),
-                       2'b0,
-                       tmp[0]};
-
-       assign rl    = {tmp[6:0],`_F[4]};
-       assign rlf   = {({tmp[6:0],`_F[4]} == 0 ? 1'b1 : 1'b0),
-                       2'b0,
-                       tmp[7]};
-
-       assign rr    = {`_F[4],tmp[7:1]};
-       assign rrf   = {({tmp[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0),
-                       2'b0,
-                       tmp[0]};
-
-       assign sla   = {tmp[6:0],1'b0};
-       assign slaf  = {(tmp[6:0] == 0 ? 1'b1 : 1'b0),
-                       2'b0,
-                       tmp[7]};
-
-       assign sra   = {tmp[7],tmp[7:1]};
-//     assign sraf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]};   now in assign srlf =
-
-       assign swap  = {tmp[3:0],tmp[7:4]};
-       assign swapf = {(tmp == 1'b0 ? 1'b1 : 1'b0),
-                       3'b0};
-
-       assign srl   = {1'b0,tmp[7:1]};
-       assign srlf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),
-                       2'b0,
-                       tmp[0]};
-       assign sraf  = srlf;
-
-       /*  Y U Q  */
-       assign {alu_res,f_res} =
-               opcode[5] ? (
-                       opcode[4] ? (
-                               opcode[3] ? {srl,srlf} : {swap,swapf}
-                       ) : (
-                               opcode[3] ? {sra,sraf} : {sla,slaf}
-                       )
-               ) : (
-                       opcode[4] ? (
-                               opcode[3] ? {rr,rrf} : {rl,rlf}
-                       ) : (
-                               opcode[3] ? {rrc,rrcf} : {rlc,rlcf}
-                       )
-               );
-
        initial begin
                `_A <= 0;
                `_B <= 0;
@@ -292,8 +233,10 @@ module GBZ80Core(
                        end
                        wr <= 0;
                        rd <= 0;
+`ifdef isim
                        address <= 16'bxxxxxxxxxxxxxxxx;        // Make it obvious if something of type has happened.
                        wdata <= 8'bxxxxxxxx;
+`endif
                        state <= `STATE_EXECUTE;
                end
                `STATE_EXECUTE: begin
@@ -306,7 +249,10 @@ module GBZ80Core(
                        `include "allinsns.v"
                        `undef EXECUTE
                        default:
+                       begin
+                               address <= {7'h78,opcode};      // Have the CPU tell you F0xx if something's gone wrong.
                                $stop;
+                       end
                        endcase
                        state <= `STATE_WRITEBACK;
                end