Add a dirty hack to make the sim pipe directly to the readout script.

[fpgaboy.git] / insn_ret-retcc.v

diff --git a/insn_ret-retcc.v b/insn_ret-retcc.v
index bad4c04d9f457df84e67b0d230cbd4d7d1008129..dab27c3ef99023b050b109758daabe7dd44fa1af 100644 (file)
--- a/insn_ret-retcc.v
+++ b/insn_ret-retcc.v
@@ -5,10 +5,10 @@
                1:      begin   // SPECIAL CASE: cycle does NOT increase linearly with ret!
                                `EXEC_INC_PC    // cycle 1 is skipped if we are not retcc
                                case (opcode[4:3])
-                               `INSN_cc_NZ:    if (registers[`REG_F][7]) `EXEC_NEWCYCLE
-                               `INSN_cc_Z:     if (~registers[`REG_F][7]) `EXEC_NEWCYCLE
-                               `INSN_cc_NC:    if (registers[`REG_F][4]) `EXEC_NEWCYCLE
-                               `INSN_cc_C:     if (~registers[`REG_F][4]) `EXEC_NEWCYCLE
+                               `INSN_cc_NZ:    if (`_F[7])  `EXEC_NEWCYCLE
+                               `INSN_cc_Z:     if (~`_F[7]) `EXEC_NEWCYCLE
+                               `INSN_cc_NC:    if (`_F[4])  `EXEC_NEWCYCLE
+                               `INSN_cc_C:     if (~`_F[4]) `EXEC_NEWCYCLE
                                endcase
                                `EXEC_READ(`_SP)        // retry the read
                        end