IP

[fpgaboy.git] / Makefile

diff --git a/Makefile b/Makefile
index 175241da2e8a3f60f9b2a02aa4763eb76039ee37..2c17e40c52805d4eb1e75b68cea8fc6171d2996a 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,19 +1,30 @@
-VLOGS = 7seg.v GBZ80Core.v insn_call-callcc.v insn_incdec16.v \
-       insn_jr-jrcc.v insn_ld_reg_hl.v insn_ld_reg_reg.v insn_nop.v \
-       insn_ret-retcc.v Interrupt.v Uart.v allinsns.v insn_alu8.v \
-       insn_di-ei.v insn_jp_hl.v insn_ldh_ac.v insn_ld_reg_imm16.v \
-       insn_ld_sp_hl.v insn_pop_reg.v insn_rst.v System.v CPUDCM.v \
-       insn_alu_a.v insn_halt.v insn_jp-jpcc.v insn_ld_hl_reg.v \
-       insn_ld_reg_imm8.v insn_ldx_ahl.v insn_push_reg.v insn_vop_intr.v \
-       Timer.v
-
-all: CoreTop_rom.svf CoreTop_diag.svf CoreTop.twr
-
-CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS) CoreTop.ucf
+VLOGS = 7seg.v Framebuffer.v core/GBZ80Core.v Interrupt.v LCDC.v Sound1.v \
+       Sound2.v Soundcore.v System.v Timer.v Uart.v Buttons.v PS2Button.v \
+       Ethernet.v
+
+VLOGS_ALL = $(VLOGS) core/insn_call-callcc.v core/insn_incdec16.v \
+       core/insn_jr-jrcc.v core/insn_ld_reg_hl.v core/insn_ld_reg_reg.v \
+       core/insn_nop.v core/insn_ret-retcc.v core/allinsns.v \
+       core/insn_alu8.v core/insn_di-ei.v core/insn_jp_hl.v \
+       core/insn_ldh_ac.v core/insn_ld_reg_imm16.v core/insn_ld_sp_hl.v \
+       core/insn_pop_reg.v core/insn_rst.v CPUDCM.v core/insn_alu_a.v \
+       core/insn_halt.v core/insn_jp-jpcc.v core/insn_ld_hl_reg.v \
+       core/insn_ld_reg_imm8.v core/insn_ldx_ahl.v core/insn_push_reg.v \
+       core/insn_vop_intr.v core/insn_ldm8_a.v core/insn_ldm16_a.v \
+       core/insn_ldbcde_a.v core/insn_alu_ext.v core/insn_bit.v \
+       core/insn_two_byte.v core/insn_incdec_reg8.v core/insn_add_hl.v \
+       core/insn_add_sp_imm8.v core/insn_ldhl_sp_imm8.v core/insn_ld_nn_sp.v \
+       core/insn_setres.v
+
+all: CoreTop.svf
+
+sim: CoreTop_isim.exe
+
+CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS_ALL) fpgaboot.hex gbboot.hex
        xst -ifn CoreTop.xst -ofn CoreTop.syr
 
 CoreTop.ngd: CoreTop.ngc foo.bmm CoreTop.ucf
-       ngdbuild -dd _ngo -uc CoreTop.ucf -nt timestamp -bm "foo.bmm" -p xc3s500e-fg320-5 "CoreTop.ngc" CoreTop.ngd
+       ngdbuild -dd _ngo -uc CoreTop.ucf -nt timestamp -p xc3s500e-fg320-5 "CoreTop.ngc" CoreTop.ngd
 
 CoreTop_map.ncd: CoreTop.ngd
        map -p xc3s500e-fg320-5 -cm area -pr off -k 4 -c 100 -o CoreTop_map.ncd CoreTop.ngd CoreTop.pcf
@@ -27,10 +38,26 @@ CoreTop.twr: CoreTop_map.ncd
 CoreTop.bit: CoreTop.ut CoreTop.ncd
        bitgen -f CoreTop.ut CoreTop.ncd
 
+netgen/par/CoreTop_timesim.v: CoreTop.twr CoreTop.ncd
+       netgen -ise FPGABoy.ise -s 5  -pcf CoreTop.pcf -sdf_anno true -sdf_path "netgen/par" -insert_glbl true -insert_pp_buffers false -w -dir netgen/par -ofmt verilog -sim CoreTop.ncd CoreTop_timesim.v
+
+netgen/par/.CoreTop_timesim.v_work: netgen/par/CoreTop_timesim.v
+       vlogcomp netgen/par/CoreTop_timesim.v
+       vlogcomp /home/joshua/projects/fpga/ise/Xilinx101/verilog/src/glbl.v
+       
+CoreTop_isim_par.exe: netgen/par/.CoreTop_timesim.v_work
+       fuse -lib simprims_ver -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o CoreTop_isim_par.exe netgen/par/CoreTop_timesim.v -top CoreTop -top glbl
+
+CoreTop_isim.exe: $(VLOGS_ALL)
+       vlogcomp -d isim $(VLOGS) 
+       fuse -t CoreTop -o CoreTop_isim.exe
+
+parsim: CoreTop_isim_par.exe
+
 %.o: %.asm
        rgbasm -o$@ $<
 
-%.bin: %.o rom.lnk
+%.bin: %.o
        echo "[Objects]" > tmp.lnk
        echo $< >> tmp.lnk
        echo "" >> tmp.lnk
@@ -39,12 +66,16 @@ CoreTop.bit: CoreTop.ut CoreTop.ncd
        xlink tmp.lnk
        rm tmp.lnk
 
-%.mem: %.bin
+%.mem: %.bin mashrom
        ./mashrom < $< > $@
 
-CoreTop_%.bit: %.mem CoreTop.bit foo_bd.bmm
-       data2mem -bm foo_bd.bmm -bd $< -bt CoreTop.bit -o b $@
+fpgaboot.hex: fpgaboot.bin mashrom
+       ./mashrom 256 < $< > $@
 
-CoreTop_%.svf: CoreTop_%.bit impact.cmd
+
+CoreTop.svf: CoreTop.bit impact.cmd
        sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd
        impact -batch tmp.cmd
+
+parsim: CoreTop
+       
\ No newline at end of file