Add DI/EI delay test. Add LD M, A.

[fpgaboy.git] / Makefile

diff --git a/Makefile b/Makefile
index 175241da2e8a3f60f9b2a02aa4763eb76039ee37..26e2289e0ed89d5d72257cf5b9ec3c29994e26d8 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -9,7 +9,7 @@ VLOGS = 7seg.v GBZ80Core.v insn_call-callcc.v insn_incdec16.v \
 
 all: CoreTop_rom.svf CoreTop_diag.svf CoreTop.twr
 
-CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS) CoreTop.ucf
+CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS)
        xst -ifn CoreTop.xst -ofn CoreTop.syr
 
 CoreTop.ngd: CoreTop.ngc foo.bmm CoreTop.ucf
@@ -27,6 +27,18 @@ CoreTop.twr: CoreTop_map.ncd
 CoreTop.bit: CoreTop.ut CoreTop.ncd
        bitgen -f CoreTop.ut CoreTop.ncd
 
+netgen/par/CoreTop_timesim.v: CoreTop.twr CoreTop.ncd
+       netgen -ise FPGABoy.ise -s 5  -pcf CoreTop.pcf -sdf_anno true -sdf_path "netgen/par" -insert_glbl true -insert_pp_buffers false -w -dir netgen/par -ofmt verilog -sim CoreTop.ncd CoreTop_timesim.v
+
+netgen/par/.CoreTop_timesim.v_work: netgen/par/CoreTop_timesim.v
+       vlogcomp netgen/par/CoreTop_timesim.v
+       vlogcomp /home/joshua/projects/fpga/ise/Xilinx101/verilog/src/glbl.v
+       
+CoreTop_isim_par.exe: netgen/par/.CoreTop_timesim.v_work
+       fuse -lib simprims_ver -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o CoreTop_isim_par.exe netgen/par/CoreTop_timesim.v -top CoreTop -top glbl
+
+parsim: CoreTop_isim_par.exe
+
 %.o: %.asm
        rgbasm -o$@ $<
 
@@ -48,3 +60,6 @@ CoreTop_%.bit: %.mem CoreTop.bit foo_bd.bmm
 CoreTop_%.svf: CoreTop_%.bit impact.cmd
        sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd
        impact -batch tmp.cmd
+
+parsim: CoreTop
+       
\ No newline at end of file