Merge andrew:/afs/andrew/usr/czl/public/FPGABoy

[fpgaboy.git] / insn_alu8.v

diff --git a/insn_alu8.v b/insn_alu8.v
index 6abcb90befbf1bc0421739c5c97c223bfbad7e47..2921b1858a3e9fdffe1b001557e3527a8e3886c4 100644 (file)
--- a/insn_alu8.v
+++ b/insn_alu8.v
@@ -1,10 +1,13 @@
 `ifdef EXECUTE
-       `INSN_ALU8: begin
-               if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0))
-                       `EXEC_READ(_HL);
+       `INSN_ALU8,`INSN_ALU8IMM: begin
+               if ((opcode[7:6] == 2'b11) && (cycle == 0)) begin       // alu8imm
+                       `EXEC_INC_PC
+                       `EXEC_READ(`_PC + 1)
+               end else if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0))
+                       `EXEC_READ(`_HL)
                else begin
-                       `EXEC_NEWCYCLE;
-                       `EXEC_INC_PC;
+                       `EXEC_NEWCYCLE
+                       `EXEC_INC_PC
                        case (opcode[2:0])
                        `INSN_reg_A:    tmp <= `_A;
                        `INSN_reg_B:    tmp <= `_B;
@@ -20,14 +23,14 @@
 `endif
 
 `ifdef WRITEBACK
-       `INSN_ALU8: begin
-               if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
+       `INSN_ALU8,`INSN_ALU8IMM: begin
+               if (((opcode[2:0] == `INSN_reg_dHL) || (opcode[7:6] == 2'b11)) && (cycle == 0)) begin
                        /* Sit on our asses. */
                end else begin          /* Actually do the computation! */
                        case (opcode[5:3])
                        `INSN_alu_ADD: begin
                                `_A <= `_A + tmp;
-                               `_F <=  { /* Z */ ((`_A + tmp) == 0) ? 1'b1 : 1'b0,
+                               `_F <=  { /* Z */ ((`_A + tmp) == 8'b0) ? 1'b1 : 1'b0,
                                          /* N */ 1'b0,
                                          /* H */ (({1'b0,`_A[3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
                                          /* C */ (({1'b0,`_A} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
@@ -36,7 +39,7 @@
                        end
                        `INSN_alu_ADC: begin
                                `_A <= `_A + tmp + {7'b0,`_F[4]};
-                               `_F <=  { /* Z */ ((`_A + tmp + {7'b0,`_F[4]}) == 0) ? 1'b1 : 1'b0,
+                               `_F <=  { /* Z */ ((`_A + tmp + {7'b0,`_F[4]}) == 8'b0) ? 1'b1 : 1'b0,
                                          /* N */ 1'b0,
                                          /* H */ (({1'b0,`_A[3:0]} + {1'b0,tmp[3:0]} + {4'b0,`_F[4]}) >> 4 == 1) ? 1'b1 : 1'b0,
                                          /* C */ (({1'b0,`_A} + {1'b0,tmp} + {8'b0,`_F[4]}) >> 8 == 1) ? 1'b1 : 1'b0,
@@ -54,7 +57,7 @@
                        end
                        `INSN_alu_SBC: begin
                                `_A <= `_A - (tmp + {7'b0,`_F[4]});
-                               `_F <=  { /* Z */ ((`_A - (tmp + {7'b0,`_F[4]})) == 0) ? 1'b1 : 1'b0,
+                               `_F <=  { /* Z */ ((`_A - (tmp + {7'b0,`_F[4]})) == 8'b0) ? 1'b1 : 1'b0,
                                          /* N */ 1'b1,
                                          /* H */ (({1'b0,tmp[3:0]} + {4'b0,`_F[4]}) > {1'b0,`_A[3:0]}) ? 1'b1 : 1'b0,
                                          /* C */ (({1'b0,tmp} + {8'b0,`_F[4]}) > {1'b0,`_A[7:0]}) ? 1'b1 : 1'b0,