Rework it all to use the new macros.

[fpgaboy.git] / insn_incdec16.v

diff --git a/insn_incdec16.v b/insn_incdec16.v
index 01f919c4014fabb932f5321a373367b781f89fe7..95e0d3824d8399b73de395cc08ac79541843d8fa 100644 (file)
--- a/insn_incdec16.v
+++ b/insn_incdec16.v
@@ -1,29 +1,15 @@
 `ifdef EXECUTE
        `INSN_INCDEC16: begin
                case (cycle)
-               0:      begin
-                               case (opcode[5:4])
-                               `INSN_reg16_BC: begin
-                                       tmp <= registers[`REG_B];
-                                       tmp2 <= registers[`REG_C];
-                               end
-                               `INSN_reg16_DE: begin
-                                       tmp <= registers[`REG_D];
-                                       tmp2 <= registers[`REG_E];
-                               end
-                               `INSN_reg16_HL: begin
-                                       tmp <= registers[`REG_H];
-                                       tmp2 <= registers[`REG_L];
-                               end
-                               `INSN_reg16_SP: begin
-                                       tmp <= registers[`REG_SPH];
-                                       tmp2 <= registers[`REG_SPL];
-                               end
-                               endcase
-                       end
+               0:      case (opcode[5:4])
+                       `INSN_reg16_BC: {tmp,tmp2} <= `_BC;
+                       `INSN_reg16_DE: {tmp,tmp2} <= `_DE;
+                       `INSN_reg16_HL: {tmp,tmp2} <= `_HL;
+                       `INSN_reg16_SP: {tmp,tmp2} <= `_SP;
+                       endcase
                1:      begin
-                               `EXEC_INC_PC;
-                               `EXEC_NEWCYCLE;
+                               `EXEC_INC_PC
+                               `EXEC_NEWCYCLE
                        end
                endcase
        end
@@ -34,26 +20,12 @@
                case (cycle)
                0:      {tmp,tmp2} <= {tmp,tmp2} +
                                (opcode[3] ? 16'hFFFF : 16'h0001);
-               1: begin
-                               case (opcode[5:4])
-                               `INSN_reg16_BC: begin
-                                       registers[`REG_B] <= tmp;
-                                       registers[`REG_C] <= tmp2;
-                               end
-                               `INSN_reg16_DE: begin
-                                       registers[`REG_D] <= tmp;
-                                       registers[`REG_E] <= tmp2;
-                               end
-                               `INSN_reg16_HL: begin
-                                       registers[`REG_H] <= tmp;
-                                       registers[`REG_L] <= tmp2;
-                               end
-                               `INSN_reg16_SP: begin
-                                       registers[`REG_SPH] <= tmp;
-                                       registers[`REG_SPL] <= tmp2;
-                               end
-                               endcase
-                       end
+               1:      case (opcode[5:4])
+                       `INSN_reg16_BC: `_BC <= {tmp,tmp2};
+                       `INSN_reg16_DE: `_DE <= {tmp,tmp2};
+                       `INSN_reg16_HL: `_HL <= {tmp,tmp2};
+                       `INSN_reg16_SP: `_SP <= {tmp,tmp2};
+                       endcase
                endcase
        end
 `endif