Readd .keep

[fpgaboy.git] / LCDC.v

diff --git a/LCDC.v b/LCDC.v
index 41b5500a1d4c9a480f016ba098e5d2a66e2d796c..444fb85b02792a7055e84f49fe356b87e2563654 100644 (file)
--- a/LCDC.v
+++ b/LCDC.v
@@ -16,12 +16,39 @@ module LCDC(
        inout [7:0] data,
        input clk,      // 8MHz clock
        input wr, rd,
-       output reg irq = 0);
+       output wire lcdcirq,
+       output wire vblankirq,
+       output wire lcdclk, lcdvs, lcdhs,
+       output wire [2:0] lcdr, lcdg, output wire [1:0] lcdb);
        
        /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
        reg clk4 = 0;
        always @(posedge clk)
                clk4 = ~clk4;
+       assign lcdclk = clk4;
+       
+       /***** Video RAM *****/
+       /* Base is 0x8000
+        *
+        * Tile data from 8000-8FFF or 8800-97FF
+        * Background tile maps 9800-9BFF or 9C00-9FFF
+        */
+       reg [7:0] tiledata [6143:0];
+       reg [7:0] bgmap1 [1023:0];
+       reg [7:0] bgmap2 [1023:0];
+       
+       /***** LCD control registers *****/
+       reg [7:0] rLCDC = 8'h91;
+       reg [7:0] rSTAT = 8'h00;
+       reg [7:0] rSCY = 8'b00;
+       reg [7:0] rSCX = 8'b00;
+       reg [7:0] rLYC = 8'b00;
+       reg [7:0] rDMA = 8'b00;
+       reg [7:0] rBGP = 8'b00;
+       reg [7:0] rOBP0 = 8'b00;
+       reg [7:0] rOBP1 = 8'b00;
+       reg [7:0] rWY = 8'b00;
+       reg [7:0] rWX = 8'b00;
        
        /***** Sync generation *****/
        
@@ -35,6 +62,10 @@ module LCDC(
         * So, X = 0~165 is HActive,
         * X = 166-372 is HBlank,
         * X = 373-455 is HWhirrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr.
+        * [02:15:10] <Judge_> LY is updated near the 0 -> 2 transition
+        * [02:15:38] <Judge_> it seems to be updated internally first before it is visible in the LY register itself
+        * [02:15:40] <Judge_> some kind of delay
+        * [02:16:19] <Judge_> iirc it is updated about 4 cycles prior to mode 2
         */
        reg [8:0] posx = 9'h000;
        reg [7:0] posy = 8'h00;
@@ -44,31 +75,51 @@ module LCDC(
                                 2'b10)
                                : 2'b01;
        
-       always @(posedge clk)
+       assign lcdvs = (posy == 153) && (posx == 455);
+       assign lcdhs = (posx == 455);
+       assign lcdr = (posx < 160) && (posy < 144) ? {posy == rLYC ? 3'b111 : 3'b000} : 3'b000;
+       assign lcdg = (posx < 160) && (posy < 144) ? {posy < rSCY ? 3'b111 : 3'b000} : 3'b000;
+       assign lcdb = (posx < 160) && (posy < 144) ? {2'b11} : 2'b00;
+       
+       reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;
+       assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);
+       assign vblankirq = (posx == 0 && posy == 153);
+       
+       always @(posedge clk4)
        begin
                if (posx == 455) begin
                        posx <= 0;
-                       if (posy == 153)
+                       if (posy == 153) begin
                                posy <= 0;
-                       else
+                               if (0 == rLYC)
+                                       lycirq <= 1;
+                       end else begin
                                posy <= posy + 1;
-               end else
+                               /* Check for vblank and generate an IRQ if needed. */
+                               if (posy == 143) begin 
+                                       mode01irq <= 1;
+                               end
+                               if ((posy + 1) == rLYC)
+                                       lycirq <= 1;
+                               
+                       end
+               end else begin
                        posx <= posx + 1;
+                       if (posx == 165)
+                               mode00irq <= 1;
+                       else if (posx == 373)
+                               mode10irq <= 1;
+                       else begin
+                               mode00irq <= 0;
+                               mode01irq <= 0;
+                               mode10irq <= 0;
+                       end
+                       lycirq <= 0;
+               end
+               
        end
   
        /***** Bus interface *****/
-       reg [7:0] rLCDC = 8'h91;
-       reg [7:0] rSTAT = 8'h00;
-       reg [7:0] rSCY = 8'b00;
-       reg [7:0] rSCX = 8'b00;
-       reg [7:0] rLYC = 8'b00;
-       reg [7:0] rDMA = 8'b00;
-       reg [7:0] rBGP = 8'b00;
-       reg [7:0] rOBP0 = 8'b00;
-       reg [7:0] rOBP1 = 8'b00;
-       reg [7:0] rWY = 8'b00;
-       reg [7:0] rWX = 8'b00;
-       
        assign data = rd ?
                        (addr == `ADDR_LCDC) ? rLCDC :
                        (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :