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[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index ec1756ebe3b6ed66c171327c5b8caa67990325e8..afa4495c2ba6f7a1e28cd79d4b04676b6df5646c 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -707,19 +707,16 @@ endmodule
 module ROM(
        input [15:0] address,
        inout [7:0] data,
+       input clk,
        input wr, rd);
 
        reg [7:0] rom [2047:0];
        initial $readmemh("rom.hex", rom);
 
        wire decode = address[15:13] == 0;
-       reg [7:0] odata;
-       wire idata = data;
+       wire [7:0] odata = rom[address[11:0]];
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
-       
-       always @(posedge rd)
-               if (decode)
-                       odata <= rom[address];
+       //assign data = rd ? odata : 8'bzzzzzzzz;
 endmodule
 
 module InternalRAM(
@@ -735,27 +732,53 @@ module InternalRAM(
        wire idata = data;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
-       reg [13:0] diq;
-       initial
-               for (diq = 0; diq < 8191; diq = diq + 1)
-                       ram[diq] = 8'h43;
-       
        always @(negedge clk)
        begin
                if (decode && rd)
                        odata <= ram[address[12:0]];
-               if (decode && wr)
+               else if (decode && wr)
                        ram[address[12:0]] <= data;
        end
 endmodule
 
-module TestBench();
-       reg clk = 0;
+//module Switches(
+//     input [15:0] address,
+//     inout [7:0] data,
+//     input clk,
+//     input wr, rd,
+//     input [7:0] switches,
+//     output reg [7:0] ledout);
+       
+//     wire decode = address == 16'hFF51;
+//     reg [7:0] odata;
+//     wire idata = data;
+//     assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+       
+//     always @(negedge clk)
+//     begin
+//             if (decode && rd)
+//                     odata <= switches;
+//             else if (decode && wr)
+//                     ledout <= data;
+//     end
+//endmodule
+
+module CoreTop(
+       input iclk,
+       output wire [7:0] leds,
+       output serio);
+       
+       wire clk;
+       IBUFG ibuf (.O(clk), .I(iclk));
+
        wire [15:0] addr;
        wire [7:0] data;
        wire wr, rd;
        
-       always #10 clk <= ~clk;
+       wire [7:0] swleds;
+       
+       assign leds = clk?{rd,wr,addr[5:0]}:data[7:0];
+
        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),
@@ -764,15 +787,61 @@ module TestBench();
                .busrd(rd));
        
        ROM rom(
-               .address(addr),
-               .data(data),
-               .wr(wr),
-               .rd(rd));
-       
-       InternalRAM ram(
                .address(addr),
                .data(data),
                .clk(clk),
                .wr(wr),
                .rd(rd));
+       
+       assign serio = 0;
 endmodule
+
+//module TestBench();
+//     reg clk = 0;
+//     wire [15:0] addr;
+//     wire [7:0] data;
+//     wire wr, rd;
+       
+//     wire [7:0] leds;
+//     wire [7:0] switches;
+       
+//     always #10 clk <= ~clk;
+//     GBZ80Core core(
+//             .clk(clk),
+//             .busaddress(addr),
+//             .busdata(data),
+//             .buswr(wr),
+//             .busrd(rd));
+       
+//     ROM rom(
+//             .clk(clk),
+//             .address(addr),
+//             .data(data),
+//             .wr(wr),
+//             .rd(rd));
+       
+//     InternalRAM ram(
+//             .address(addr),
+//             .data(data),
+//             .clk(clk),
+//             .wr(wr),
+//             .rd(rd));
+
+//     wire serio;
+//     UART uart(
+//             .addr(addr),
+//             .data(data),
+//             .clk(clk),
+//             .wr(wr),
+//             .rd(rd),
+//             .serial(serio));
+       
+//     Switches sw(
+//             .clk(clk),
+//             .address(addr),
+//             .data(data),
+//             .wr(wr),
+//             .rd(rd),
+//             .switches(switches),
+//             .leds(leds));
+//endmodule