+module Switches(
+ input [15:0] address,
+ inout [7:0] data,
+ input clk,
+ input wr, rd,
+ input [7:0] switches,
+ output reg [7:0] ledout);
+
+ wire decode = address == 16'hFF51;
+ reg [7:0] odata;
+ wire idata = data;
+ assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+
+ always @(negedge clk)
+ begin
+ if (decode && rd)
+ odata <= switches;
+ else if (decode && wr)
+ ledout <= data;
+ end
+endmodule
+
+module CoreTop(
+ input xtal,
+ input [1:0] switches,
+ output wire [7:0] leds,
+ output serio,
+ output wire [3:0] digits,
+ output wire [7:0] seven);
+
+ wire clk;
+ //IBUFG ibuf (.O(clk), .I(iclk));
+
+ CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
+