Ethernet TX support

[fpgaboy.git] / core / GBZ80Core.v

diff --git a/core/GBZ80Core.v b/core/GBZ80Core.v
index b5a502cefeef17761325ff3066699b1eef174214..4a1e25675b4db43a24903c202065b0b32d38cb68 100644 (file)
--- a/core/GBZ80Core.v
+++ b/core/GBZ80Core.v
@@ -233,8 +233,10 @@ module GBZ80Core(
                        end
                        wr <= 0;
                        rd <= 0;
                        end
                        wr <= 0;
                        rd <= 0;

+`ifdef isim

                        address <= 16'bxxxxxxxxxxxxxxxx;        // Make it obvious if something of type has happened.
                        wdata <= 8'bxxxxxxxx;
                        address <= 16'bxxxxxxxxxxxxxxxx;        // Make it obvious if something of type has happened.
                        wdata <= 8'bxxxxxxxx;

+`endif

                        state <= `STATE_EXECUTE;
                end
                `STATE_EXECUTE: begin
                        state <= `STATE_EXECUTE;
                end
                `STATE_EXECUTE: begin


@@ -247,7 +249,10 @@ module GBZ80Core(
                        `include "allinsns.v"
                        `undef EXECUTE
                        default:
                        `include "allinsns.v"
                        `undef EXECUTE
                        default:

+                       begin
+                               address <= {7'h78,opcode};      // Have the CPU tell you F0xx if something's gone wrong.

                                $stop;
                                $stop;

+                       end

                        endcase
                        state <= `STATE_WRITEBACK;
                end
                        endcase
                        state <= `STATE_WRITEBACK;
                end