reg [7:0] progaddrh, progaddrm, progaddrl;
+ reg [22:0] progaddr;
+
assign cr_nADV = 0; /* Addresses are always valid! :D */
assign cr_nCE = 0; /* The chip is enabled */
assign cr_nLB = 0; /* Lower byte is enabled */
assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom */ {9'b0,addrlatch[13:0]} :
(addrlatch[15:13] == 3'b101) ? {1'b1, 9'b0, addrlatch[12:0]} :
- (addrlatch == ADDR_PROGDATA) ? {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} :
+ (addrlatch == ADDR_PROGDATA) ? progaddr :
23'b0;
reg [7:0] regbuf;
ADDR_PROGADDRH: if (wr) progaddrh <= data;
ADDR_PROGADDRM: if (wr) progaddrm <= data;
ADDR_PROGADDRL: if (wr) progaddrl <= data;
+ ADDR_PROGDATA: if (rd || wr) begin
+ progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]};
+ {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]} + 23'b1;
+ end
endcase
rdlatch <= rd;
wrlatch <= wr;