Latest shit, I can't remember
[fpgaboy.git] / System.v
index 55dda1c..c2e892b 100644 (file)
--- a/System.v
+++ b/System.v
@@ -1,6 +1,6 @@
 
 `timescale 1ns / 1ps
-module ROM(
+module SimROM(
        input [15:0] address,
        inout [7:0] data,
        input clk,
@@ -9,8 +9,7 @@ module ROM(
        reg rdlatch = 0;
        reg [7:0] odata;
 
-       // synthesis attribute ram_style of rom is block
-       reg [7:0] rom [1023:0];
+       reg [7:0] rom [32767:0];
        initial $readmemh("rom.hex", rom);
 
        wire decode = address[15:13] == 0;
@@ -35,6 +34,10 @@ module BootstrapROM(
        
        initial $readmemh("fpgaboot.hex", brom0);
        initial $readmemh("gbboot.hex", brom1);
+       
+`ifdef isim
+       initial romno <= 1;
+`endif
 
        wire decode = address[15:8] == 0;
        wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
@@ -85,6 +88,7 @@ module CellularRAM(
        parameter ADDR_PROGADDRM = 16'hFF61;
        parameter ADDR_PROGADDRL = 16'hFF62;
        parameter ADDR_PROGDATA = 16'hFF63;
+       parameter ADDR_MBC = 16'hFF64;
        
        reg rdlatch = 0, wrlatch = 0;
        reg [15:0] addrlatch = 0;
@@ -94,6 +98,9 @@ module CellularRAM(
        
        reg [22:0] progaddr;
        
+       reg [7:0] mbc_emul = 8'b00000101;       // High bit is whether we're poking flash
+                                               // low 7 bits are the MBC that we are emulating
+       
        assign cr_nADV = 0;     /* Addresses are always valid! :D */
        assign cr_nCE = 0;      /* The chip is enabled */
        assign cr_nLB = 0;      /* Lower byte is enabled */
@@ -103,17 +110,19 @@ module CellularRAM(
        
        wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
        
+       reg [3:0] rambank = 0;
+       reg [8:0] rombank = 1;
+       
        assign cr_nOE = decode ? ~rdlatch : 1;
-       assign cr_nWE = decode ? ~wrlatch : 1;
+       assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (mbc_emul[6:0] == 0))) ? ~wrlatch : 1;
        
        assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
-       assign cr_A = (address[15:14] == 2'b00) ? /* extrom */ {9'b0,address[13:0]} :
-                       (address[15:13] == 3'b101) ? {1'b1, 9'b0, address[12:0]} :
-                       (address == ADDR_PROGDATA) ? progaddr :
+       assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :
+                       (addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} :
+                       (addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} :
+                       (addrlatch == ADDR_PROGDATA) ? progaddr :
                        23'b0;
        
-       reg [7:0] regbuf;
-       
        always @(posedge clk) begin
                case (address)
                ADDR_PROGADDRH: if (wr) progaddrh <= data;
@@ -123,7 +132,22 @@ module CellularRAM(
                                        progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
                                        {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
                                end
+               ADDR_MBC:       begin
+                                       mbc_emul <= data;
+                                       rambank <= 0;
+                                       rombank <= 1;
+                               end
                endcase
+               
+               if (mbc_emul[6:0] == 5) begin
+                       if ((address[15:12] == 4'h2) && wr)
+                               rombank <= {rombank[8], data};
+                       else if ((address[15:12] == 4'h3) && wr)
+                               rombank <= {data[0], rombank[7:0]};
+                       else if ((address[15:12] == 4'h4) && wr)
+                               rambank <= data[3:0];
+               end
+               
                rdlatch <= rd;
                wrlatch <= wr;
                addrlatch <= address;
@@ -264,7 +288,7 @@ module CoreTop(
                .rd(rd[1]));
        
 `ifdef isim
-       ROM rom(
+       SimROM rom(
                .address(addr[0]),
                .data(data[0]),
                .clk(clk),
@@ -321,7 +345,17 @@ module CoreTop(
                .vgar(r),
                .vgag(g),
                .vgab(b));
-       
+
+       Switches sw(
+               .clk(clk),
+               .address(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),
+               .ledout(leds),
+               .switches(switches)
+               );
+
        AddrMon amon(
                .clk(clk), 
                .addr(addr[0]),
@@ -334,16 +368,6 @@ module CoreTop(
                        (state == 2'b10) ? 4'b1000 :
                                           4'b0100) );
         
-       Switches sw(
-               .clk(clk),
-               .address(addr[0]),
-               .data(data[0]),
-               .wr(wr[0]),
-               .rd(rd[0]),
-               .ledout(leds),
-               .switches(switches)
-               );
-
        UART nouart (   /* no u */
                .clk(clk),
                .addr(addr[0]),
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