Finish splitting out functions.

[fpgaboy.git] / insn_incdec16.v

diff --git a/insn_incdec16.v b/insn_incdec16.v
new file mode 100644 (file)
index 0000000..01f919c
--- /dev/null
+++ b/insn_incdec16.v
@@ -0,0 +1,59 @@
+`ifdef EXECUTE
+       `INSN_INCDEC16: begin
+               case (cycle)
+               0:      begin
+                               case (opcode[5:4])
+                               `INSN_reg16_BC: begin
+                                       tmp <= registers[`REG_B];
+                                       tmp2 <= registers[`REG_C];
+                               end
+                               `INSN_reg16_DE: begin
+                                       tmp <= registers[`REG_D];
+                                       tmp2 <= registers[`REG_E];
+                               end
+                               `INSN_reg16_HL: begin
+                                       tmp <= registers[`REG_H];
+                                       tmp2 <= registers[`REG_L];
+                               end
+                               `INSN_reg16_SP: begin
+                                       tmp <= registers[`REG_SPH];
+                                       tmp2 <= registers[`REG_SPL];
+                               end
+                               endcase
+                       end
+               1:      begin
+                               `EXEC_INC_PC;
+                               `EXEC_NEWCYCLE;
+                       end
+               endcase
+       end
+`endif
+
+`ifdef WRITEBACK
+       `INSN_INCDEC16: begin
+               case (cycle)
+               0:      {tmp,tmp2} <= {tmp,tmp2} +
+                               (opcode[3] ? 16'hFFFF : 16'h0001);
+               1: begin
+                               case (opcode[5:4])
+                               `INSN_reg16_BC: begin
+                                       registers[`REG_B] <= tmp;
+                                       registers[`REG_C] <= tmp2;
+                               end
+                               `INSN_reg16_DE: begin
+                                       registers[`REG_D] <= tmp;
+                                       registers[`REG_E] <= tmp2;
+                               end
+                               `INSN_reg16_HL: begin
+                                       registers[`REG_H] <= tmp;
+                                       registers[`REG_L] <= tmp2;
+                               end
+                               `INSN_reg16_SP: begin
+                                       registers[`REG_SPH] <= tmp;
+                                       registers[`REG_SPL] <= tmp2;
+                               end
+                               endcase
+                       end
+               endcase
+       end
+`endif