alu_ext

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index f41805ac3c679aeebded8c8d2014f921fe8931c0..45870d195f581fc91d2fe6617f1200789f3ab98c 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -1,59 +1,89 @@
-`define REG_A 0
-`define REG_B 1
-`define REG_C 2
-`define REG_D 3
-`define REG_E 4
-`define REG_F 5
-`define REG_H 6
-`define REG_L 7
-`define REG_SPH 8
-`define REG_SPL 9
-`define REG_PCH 10
-`define REG_PCL 11
+`define REG_A  0
+`define REG_B  1
+`define REG_C  2
+`define REG_D  3
+`define REG_E  4
+`define REG_F  5
+`define REG_H  6
+`define REG_L  7
+`define REG_SPH        8
+`define REG_SPL        9
+`define REG_PCH        10
+`define REG_PCL        11

 
 

-`define FLAG_Z 8'b10000000
-`define FLAG_N 8'b01000000
-`define FLAG_H 8'b00100000
-`define FLAG_C 8'b00010000
+`define _A     registers[`REG_A]
+`define _B     registers[`REG_B]
+`define _C     registers[`REG_C]
+`define _D     registers[`REG_D]
+`define _E     registers[`REG_E]
+`define _F     registers[`REG_F]
+`define _H     registers[`REG_H]
+`define _L     registers[`REG_L]
+`define _SPH   registers[`REG_SPH]
+`define _SPL   registers[`REG_SPL]
+`define _PCH   registers[`REG_PCH]
+`define _PCL   registers[`REG_PCL]
+`define _AF    {`_A, `_F}
+`define _BC    {`_B, `_C}
+`define _DE    {`_D, `_E}
+`define _HL    {`_H, `_L}
+`define _SP    {`_SPH, `_SPL}
+`define _PC    {`_PCH, `_PCL}

 
 

-`define STATE_FETCH                    2'h0
-`define STATE_DECODE                   2'h1
+`define FLAG_Z 8'b10000000
+`define FLAG_N 8'b01000000
+`define FLAG_H 8'b00100000
+`define FLAG_C 8'b00010000
+
+`define STATE_FETCH            2'h0
+`define STATE_DECODE           2'h1

 `define STATE_EXECUTE          2'h2
 `define STATE_WRITEBACK                2'h3
 
 `define STATE_EXECUTE          2'h2
 `define STATE_WRITEBACK                2'h3
 

-`define INSN_LD_reg_imm8       8'b00xxx110
-`define INSN_HALT                              8'b01110110
-`define INSN_LD_HL_reg         8'b01110xxx
-`define INSN_LD_reg_HL         8'b01xxx110
-`define INSN_LD_reg_reg                8'b01xxxxxx
-`define INSN_LD_reg_imm16      8'b00xx0001
-`define INSN_LD_SP_HL          8'b11111001
-`define INSN_PUSH_reg          8'b11xx0101
-`define INSN_POP_reg                   8'b11xx0001
-`define INSN_LDH_AC                    8'b111x0010     // Either LDH A,(C) or LDH (C),A
-`define INSN_LDx_AHL                   8'b001xx010     // LDD/LDI A,(HL) / (HL),A
-`define INSN_ALU8                              8'b10xxxxxx     // 10 xxx yyy
-`define INSN_NOP                               8'b00000000
-`define INSN_RST                               8'b11xxx111
-`define INSN_RET                               8'b110x1001     // 1 = RETI, 0 = RET
-`define INSN_RETCC                     8'b110xx000
-`define INSN_CALL                              8'b11001101
-`define INSN_CALLCC                    8'b110xx100     // Not that call/cc.
-`define INSN_JP_imm                    8'b11000011
-`define INSN_JPCC_imm          8'b110xx010
-`define INSN_ALU_A             8'b00xxx111
-`define INSN_JP_HL                     8'b11101001
-`define INSN_JR_imm                    8'b00011000
-`define INSN_JRCC_imm          8'b001xx000
-`define INSN_INCDEC16          8'b00xxx011
-`define INSN_VOP_INTR          8'b11111100     // 0xFC is grabbed by the fetch if there is an interrupt pending.
-`define INSN_DI                                8'b11110011
-`define INSN_EI                                8'b11111011
+`define INSN_LD_reg_imm8       9'b000xxx110
+`define INSN_HALT              9'b001110110
+`define INSN_LD_HL_reg         9'b001110xxx
+`define INSN_LD_reg_HL         9'b001xxx110
+`define INSN_LD_reg_reg                9'b001xxxxxx
+`define INSN_LD_reg_imm16      9'b000xx0001
+`define INSN_LD_SP_HL          9'b011111001
+`define INSN_PUSH_reg          9'b011xx0101
+`define INSN_POP_reg           9'b011xx0001
+`define INSN_LDH_AC            9'b0111x0010    // Either LDH A,(C) or LDH (C),A
+`define INSN_LDx_AHL           9'b0001xx010    // LDD/LDI A,(HL) / (HL),A
+`define INSN_ALU8              9'b010xxxxxx    // 10 xxx yyy
+`define INSN_ALU8IMM           9'b011xxx110
+`define INSN_NOP               9'b000000000
+`define INSN_RST               9'b011xxx111
+`define INSN_RET               9'b0110x1001    // 1 = RETI, 0 = RET
+`define INSN_RETCC             9'b0110xx000
+`define INSN_CALL              9'b011001101
+`define INSN_CALLCC            9'b0110xx100    // Not that call/cc.
+`define INSN_JP_imm            9'b011000011
+`define INSN_JPCC_imm          9'b0110xx010
+`define INSN_ALU_A             9'b000xxx111
+`define INSN_JP_HL             9'b011101001
+`define INSN_JR_imm            9'b000011000
+`define INSN_JRCC_imm          9'b0001xx000
+`define INSN_INCDEC16          9'b000xxx011
+`define INSN_VOP_INTR          9'b011111100    // 0xFC is grabbed by the fetch if there is an interrupt pending.
+`define INSN_DI                        9'b011110011
+`define INSN_EI                        9'b011111011
+`define INSN_INCDEC_HL         9'b00011010x
+`define INSN_INCDEC_reg8       9'b000xxx10x
+`define INSN_LD8M_A            9'b0111x0000    // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
+`define INSN_LD16M_A           9'b0111x1010    // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
+`define INSN_LDBCDE_A          9'b0000xx010
+`define INSN_TWO_BYTE          9'b011001011    // prefix for two-byte opqodes
+`define INSN_ALU_EXT           9'b100xxxxxx
+`define INSN_BIT               9'b101xxxxxx
+`define INSN_RES               9'b110xxxxxx
+`define INSN_SET               9'b111xxxxxx

 
 

-`define INSN_cc_NZ                     2'b00
-`define INSN_cc_Z                              2'b01
-`define INSN_cc_NC                     2'b10
-`define INSN_cc_C                              2'b11
+`define INSN_cc_NZ             2'b00
+`define INSN_cc_Z              2'b01
+`define INSN_cc_NC             2'b10
+`define INSN_cc_C              2'b11

 
 `define INSN_reg_A             3'b111
 `define INSN_reg_B             3'b000
 
 `define INSN_reg_A             3'b111
 `define INSN_reg_B             3'b000


@@ -62,15 +92,15 @@
 `define INSN_reg_E             3'b011
 `define INSN_reg_H             3'b100
 `define INSN_reg_L             3'b101
 `define INSN_reg_E             3'b011
 `define INSN_reg_H             3'b100
 `define INSN_reg_L             3'b101

-`define INSN_reg_dHL   3'b110
-`define INSN_reg16_BC  2'b00
-`define INSN_reg16_DE  2'b01
-`define INSN_reg16_HL  2'b10
-`define INSN_reg16_SP  2'b11
-`define INSN_stack_AF  2'b11
-`define INSN_stack_BC  2'b00
-`define INSN_stack_DE  2'b01
-`define INSN_stack_HL  2'b10
+`define INSN_reg_dHL           3'b110
+`define INSN_reg16_BC          2'b00
+`define INSN_reg16_DE          2'b01
+`define INSN_reg16_HL          2'b10
+`define INSN_reg16_SP          2'b11
+`define INSN_stack_AF          2'b11
+`define INSN_stack_BC          2'b00
+`define INSN_stack_DE          2'b01
+`define INSN_stack_HL          2'b10

 `define INSN_alu_ADD           3'b000
 `define INSN_alu_ADC           3'b001
 `define INSN_alu_SUB           3'b010
 `define INSN_alu_ADD           3'b000
 `define INSN_alu_ADC           3'b001
 `define INSN_alu_SUB           3'b010


@@ -87,33 +117,108 @@
 `define INSN_alu_CPL           3'b101
 `define INSN_alu_SCF           3'b110
 `define INSN_alu_CCF           3'b111
 `define INSN_alu_CPL           3'b101
 `define INSN_alu_SCF           3'b110
 `define INSN_alu_CCF           3'b111

+`define INSN_alu_RLC           3'b000
+`define INSN_alu_RRC           3'b001
+`define INSN_alu_RL            3'b010
+`define INSN_alu_RR            3'b011
+`define INSN_alu_DA_SLA                3'b100
+`define INSN_alu_CPL_SRA       3'b101
+`define INSN_alu_SCF_SWAP      3'b110
+`define INSN_alu_CCF_SRL       3'b111
+
+`define EXEC_INC_PC            `_PC <= `_PC + 1;
+`define EXEC_NEXTADDR_PCINC    address <= `_PC + 1;
+`define EXEC_NEWCYCLE          begin newcycle <= 1; rd <= 1; wr <= 0; end
+`define EXEC_NEWCYCLE_TWOBYTE  begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end
+`define EXEC_WRITE(ad, da)     begin address <= (ad); wdata <= (da); wr <= 1; end end
+`define EXEC_READ(ad)          begin address <= (ad); rd <= 1; end end

 
 module GBZ80Core(
        input clk,
        output reg [15:0] busaddress,   /* BUS_* is latched on STATE_FETCH. */
        inout [7:0] busdata,
        output reg buswr, output reg busrd,
 
 module GBZ80Core(
        input clk,
        output reg [15:0] busaddress,   /* BUS_* is latched on STATE_FETCH. */
        inout [7:0] busdata,
        output reg buswr, output reg busrd,

-       input irq, input [7:0] jaddr);
-       
-       reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */
+       input irq, input [7:0] jaddr,
+       output reg [1:0] state);
+
+//     reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */

        reg [2:0] cycle;                                        /* Cycle for instructions. */
        
        reg [7:0] registers[11:0];
        
        reg [15:0] address;                             /* Address for the next bus operation. */
        
        reg [2:0] cycle;                                        /* Cycle for instructions. */
        
        reg [7:0] registers[11:0];
        
        reg [15:0] address;                             /* Address for the next bus operation. */
        

-       reg [7:0] opcode;                               /* Opcode from the current machine cycle. */
-       
+       reg [8:0] opcode;                               /* Opcode from the current machine cycle. */
+

        reg [7:0] rdata, wdata;         /* Read data from this bus cycle, or write data for the next. */
        reg [7:0] rdata, wdata;         /* Read data from this bus cycle, or write data for the next. */

-       reg rd, wr, newcycle;
+       reg rd, wr, newcycle, twobyte;

        
        reg [7:0] tmp, tmp2;                    /* Generic temporary regs. */
        
        reg [7:0] buswdata;
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
        
        reg [7:0] tmp, tmp2;                    /* Generic temporary regs. */
        
        reg [7:0] buswdata;
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;

-       
+

        reg ie, iedelay;
        reg ie, iedelay;

-       
+
+       wire [7:0] rlc,rrc,rl,rr,sla,sra,swap,srl;
+       wire [3:0] rlcf,rrcf,rlf,rrf,slaf,sraf,swapf,srlf;
+       wire [7:0] alu_res;
+       wire [3:0] f_res;
+
+       assign rlc   = {tmp[6:0],tmp[7]};
+       assign rlcf  = {(tmp == 0 ? 1'b1 : 1'b0)
+                       ,2'b0,
+                       tmp[7]};
+
+       assign rrc   = {tmp[0],tmp[7:1]};
+       assign rrcf  = {(tmp == 0 ? 1'b1 : 1'b0),
+                       2'b0,
+                       tmp[0]};
+
+       assign rl    = {tmp[6:0],`_F[4]};
+       assign rlf   = {({tmp[6:0],`_F[4]} == 0 ? 1'b1 : 1'b0),
+                       2'b0,
+                       tmp[7]};
+
+       assign rr    = {`_F[4],tmp[7:1]};
+       assign rrf   = {({tmp[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0),
+                       2'b0,
+                       tmp[0]};
+
+       assign sla   = {tmp[6:0],0};
+       assign slaf  = {(tmp[6:0] == 0 ? 1'b1 : 1'b0),
+                       2'b0,
+                       tmp[7]};
+
+       assign sra   = {tmp[7],tmp[7:1]};
+//     assign sraf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]};   now in assign srlf =
+
+       assign swap  = {tmp[3:0],tmp[7:4]};
+       assign swapf = {(tmp == 0 ? 1'b1 : 1'b0),
+                       3'b0};
+
+       assign srl   = {0,tmp[7:1]};
+       assign srlf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),
+                       2'b0,
+                       tmp[0]};
+       assign sraf  = srlf;
+
+       /*  Y U Q  */
+       assign {alu_res,f_res} =
+               opcode[5] ? (
+                       opcode[4] ? (
+                               opcode[3] ? {srl,srlf} : {swap,swapf}
+                       ) : (
+                               opcode[3] ? {sra,sraf} : {sla,slaf}
+                       )
+               ) : (
+                       opcode[4] ? (
+                               opcode[3] ? {rr,rrf} : {rl,rlf}
+                       ) : (
+                               opcode[3] ? {rrc,rrcf} : {rlc,rlcf}
+                       )
+               );
+

        initial begin
                registers[ 0] <= 0;
                registers[ 1] <= 0;
        initial begin
                registers[ 0] <= 0;
                registers[ 1] <= 0;


@@ -140,13 +245,14 @@ module GBZ80Core(
                opcode <= 0;
                state <= `STATE_WRITEBACK;
                cycle <= 0;
                opcode <= 0;
                state <= `STATE_WRITEBACK;
                cycle <= 0;

+               twobyte <= 0;

        end
 
        always @(posedge clk)
                case (state)
                `STATE_FETCH: begin
                        if (newcycle) begin
        end
 
        always @(posedge clk)
                case (state)
                `STATE_FETCH: begin
                        if (newcycle) begin

-                               busaddress <= {registers[`REG_PCH], registers[`REG_PCL]};
+                               busaddress <= `_PC;

                                buswr <= 0;
                                busrd <= 1;
                        end else begin
                                buswr <= 0;
                                busrd <= 1;
                        end else begin


@@ -160,10 +266,13 @@ module GBZ80Core(
                end
                `STATE_DECODE: begin
                        if (newcycle) begin
                end
                `STATE_DECODE: begin
                        if (newcycle) begin

-                               if (ie && irq)
+                               if (twobyte) begin
+                                       opcode <= {1,busdata};
+                                       twobyte <= 0;
+                               end else if (ie && irq)

                                        opcode <= `INSN_VOP_INTR;
                                else
                                        opcode <= `INSN_VOP_INTR;
                                else

-                                       opcode <= busdata;
+                                       opcode <= {0,busdata};

                                rdata <= busdata;
                                newcycle <= 0;
                                cycle <= 0;
                                rdata <= busdata;
                                newcycle <= 0;
                                cycle <= 0;


@@ -184,213 +293,10 @@ module GBZ80Core(
                        state <= `STATE_EXECUTE;
                end
                `STATE_EXECUTE: begin
                        state <= `STATE_EXECUTE;
                end
                `STATE_EXECUTE: begin

-`define EXEC_INC_PC \
-       {registers[`REG_PCH], registers[`REG_PCL]} <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
-`define EXEC_NEXTADDR_PCINC \
-       address <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
-`define EXEC_NEWCYCLE \
-       newcycle <= 1; rd <= 1; wr <= 0

                        casex (opcode)
                        `define EXECUTE
                        `include "allinsns.v"
                        `undef EXECUTE
                        casex (opcode)
                        `define EXECUTE
                        `include "allinsns.v"
                        `undef EXECUTE

-                       `INSN_RST: begin
-                               case (cycle)
-                               0:      begin
-                                               `EXEC_INC_PC;           // This goes FIRST in RST
-                                       end
-                               1:      begin
-                                               wr <= 1;
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
-                                               wdata <= registers[`REG_PCH];
-                                       end
-                               2:      begin
-                                               wr <= 1;
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
-                                               wdata <= registers[`REG_PCL];
-                                       end
-                               3:      begin
-                                               `EXEC_NEWCYCLE;
-                                               {registers[`REG_PCH],registers[`REG_PCL]} <=
-                                                       {10'b0,opcode[5:3],3'b0};
-                                       end
-                               endcase
-                       end
-                       `INSN_RET,`INSN_RETCC: begin
-                               case (cycle)
-                               0:      begin
-                                               rd <= 1;
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
-                                       end
-                               1:      begin   // SPECIAL CASE: cycle does NOT increase linearly with ret!
-                                               `EXEC_INC_PC;   // cycle 1 is skipped if we are not retcc
-                                               case (opcode[4:3])
-                                               `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
-                                               `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
-                                               `INSN_cc_NC:    if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
-                                               `INSN_cc_C:             if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
-                                               endcase
-                                               rd <= 1;
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
-                                       end
-                               2:      begin
-                                               rd <= 1;
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
-                                       end
-                               3:      begin /* twiddle thumbs */ end
-                               4:      begin
-                                               `EXEC_NEWCYCLE;
-                                               // do NOT increment PC!
-                                       end
-                               endcase
-                       end
-                       `INSN_CALL,`INSN_CALLCC: begin
-                               case (cycle)
-                               0:      begin
-                                               `EXEC_INC_PC;
-                                               `EXEC_NEXTADDR_PCINC;
-                                               rd <= 1;
-                                       end
-                               1:      begin
-                                               `EXEC_INC_PC;
-                                               `EXEC_NEXTADDR_PCINC;
-                                               rd <= 1;
-                                       end
-                               2:      begin
-                                               `EXEC_INC_PC;
-                                               if (!opcode[0]) // i.e., is callcc
-                                                       /* We need to check the condition code to bail out. */
-                                                       case (opcode[4:3])
-                                                       `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
-                                                       `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
-                                                       `INSN_cc_NC:    if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
-                                                       `INSN_cc_C:             if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
-                                                       endcase
-                                       end
-                               3:      begin
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
-                                               wdata <= registers[`REG_PCH];
-                                               wr <= 1;
-                                       end
-                               4:      begin
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
-                                               wdata <= registers[`REG_PCL];
-                                               wr <= 1;
-                                       end
-                               5:      begin
-                                               `EXEC_NEWCYCLE; /* do NOT increment the PC */
-                                       end
-                               endcase
-                       end
-                       `INSN_JP_imm,`INSN_JPCC_imm: begin
-                               case (cycle)
-                               0:      begin
-                                               `EXEC_INC_PC;
-                                               `EXEC_NEXTADDR_PCINC;
-                                               rd <= 1;
-                                       end
-                               1:      begin
-                                               `EXEC_INC_PC;
-                                               `EXEC_NEXTADDR_PCINC;
-                                               rd <= 1;
-                                       end
-                               2:      begin
-                                               `EXEC_INC_PC;
-                                               if (!opcode[0]) begin   // i.e., JP cc,nn
-                                                       /* We need to check the condition code to bail out. */
-                                                       case (opcode[4:3])
-                                                       `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
-                                                       `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
-                                                       `INSN_cc_NC:    if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
-                                                       `INSN_cc_C:             if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
-                                                       endcase
-                                               end
-                                       end
-                               3:      begin
-                                               `EXEC_NEWCYCLE;
-                                       end
-                               endcase
-                       end
-                       `INSN_JP_HL: begin
-                               `EXEC_NEWCYCLE;
-                       end
-                       `INSN_JR_imm,`INSN_JRCC_imm: begin
-                               case (cycle)
-                               0:      begin
-                                               `EXEC_INC_PC;
-                                               `EXEC_NEXTADDR_PCINC;
-                                               rd <= 1;
-                                       end
-                               1: begin
-                                               `EXEC_INC_PC;
-                                               if (opcode[5]) begin    // i.e., JP cc,nn
-                                                       /* We need to check the condition code to bail out. */
-                                                       case (opcode[4:3])
-                                                       `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
-                                                       `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
-                                                       `INSN_cc_NC:    if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
-                                                       `INSN_cc_C:             if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
-                                                       endcase
-                                               end
-                                       end
-                               2:      begin
-                                               `EXEC_NEWCYCLE;
-                                       end
-                               endcase
-                       end
-                       `INSN_INCDEC16: begin
-                               case (cycle)
-                               0: begin
-                                               case (opcode[5:4])
-                                               `INSN_reg16_BC: begin
-                                                       tmp <= registers[`REG_B];
-                                                       tmp2 <= registers[`REG_C];
-                                               end
-                                               `INSN_reg16_DE: begin
-                                                       tmp <= registers[`REG_D];
-                                                       tmp2 <= registers[`REG_E];
-                                               end
-                                               `INSN_reg16_HL: begin
-                                                       tmp <= registers[`REG_H];
-                                                       tmp2 <= registers[`REG_L];
-                                               end
-                                               `INSN_reg16_SP: begin
-                                                       tmp <= registers[`REG_SPH];
-                                                       tmp2 <= registers[`REG_SPL];
-                                               end
-                                               endcase
-                                       end
-                               1: begin
-                                               `EXEC_INC_PC;
-                                               `EXEC_NEWCYCLE;
-                                       end
-                               endcase
-                       end
-                       `INSN_VOP_INTR: begin
-                               case (cycle)
-                               0:      begin
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
-                                               wdata <= registers[`REG_PCH];
-                                               wr <= 1;
-                                       end
-                               1:      begin
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
-                                               wdata <= registers[`REG_PCL];
-                                               wr <= 1;
-                                       end
-                               2:      begin
-                                               `EXEC_NEWCYCLE;
-                                       end
-                               endcase
-                       end
-                       `INSN_DI: begin
-                               `EXEC_NEWCYCLE;
-                               `EXEC_INC_PC;
-                       end
-                       `INSN_EI: begin
-                               `EXEC_NEWCYCLE;
-                               `EXEC_INC_PC;
-                       end

                        default:
                                $stop;
                        endcase
                        default:
                                $stop;
                        endcase


@@ -401,107 +307,6 @@ module GBZ80Core(
                        `define WRITEBACK
                        `include "allinsns.v"
                        `undef WRITEBACK
                        `define WRITEBACK
                        `include "allinsns.v"
                        `undef WRITEBACK

-                       `INSN_RST: begin
-                               case (cycle)
-                               0:      begin /* type F */ end
-                               1:      begin /* type F */ end
-                               2:      begin /* type F */ end
-                               3:      {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                               {registers[`REG_SPH],registers[`REG_SPL]}-2;
-                               endcase
-                       end
-                       `INSN_RET,`INSN_RETCC: begin
-                               case (cycle)
-                               0:      if (opcode[0])  // i.e., not RETCC
-                                               cycle <= 1;     // Skip cycle 1; it gets incremented on the next round.
-                               1: begin /* Nothing need happen here. */ end
-                               2:      registers[`REG_PCL] <= rdata;
-                               3:      registers[`REG_PCH] <= rdata;
-                               4:      begin
-                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                                       {registers[`REG_SPH],registers[`REG_SPL]} + 2;
-                                               if (opcode[4] && opcode[0])     /* RETI */
-                                                       ie <= 1;
-                                       end
-                               endcase
-                       end
-                       `INSN_CALL,`INSN_CALLCC: begin
-                               case (cycle)
-                               0:      begin /* type F */ end
-                               1:      tmp <= rdata;   // tmp contains newpcl
-                               2:      tmp2 <= rdata;  // tmp2 contains newpch
-                               3:      begin /* type F */ end
-                               4:      registers[`REG_PCH] <= tmp2;
-                               5: begin
-                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                                       {registers[`REG_SPH],registers[`REG_SPL]} - 2;
-                                               registers[`REG_PCL] <= tmp;
-                                       end
-                               endcase
-                       end
-                       `INSN_JP_imm,`INSN_JPCC_imm: begin
-                               case (cycle)
-                               0:      begin /* type F */ end
-                               1:      tmp <= rdata;   // tmp contains newpcl
-                               2:      tmp2 <= rdata;  // tmp2 contains newpch
-                               3:      {registers[`REG_PCH],registers[`REG_PCL]} <=
-                                               {tmp2,tmp};
-                               endcase
-                       end
-                       `INSN_JP_HL: begin
-                               {registers[`REG_PCH],registers[`REG_PCL]} <=
-                                       {registers[`REG_H],registers[`REG_L]};
-                       end
-                       `INSN_JR_imm,`INSN_JRCC_imm: begin
-                               case (cycle)
-                               0:      begin /* type F */ end
-                               1:      tmp <= rdata;
-                               2: {registers[`REG_PCH],registers[`REG_PCL]} <=
-                                               {registers[`REG_PCH],registers[`REG_PCL]} +
-                                               {tmp[7]?8'hFF:8'h00,tmp};
-                               endcase
-                       end
-                       `INSN_INCDEC16: begin
-                               case (cycle)
-                               0:      {tmp,tmp2} <= {tmp,tmp2} +
-                                               (opcode[3] ? 16'hFFFF : 16'h0001);
-                               1: begin
-                                               case (opcode[5:4])
-                                               `INSN_reg16_BC: begin
-                                                       registers[`REG_B] <= tmp;
-                                                       registers[`REG_C] <= tmp2;
-                                               end
-                                               `INSN_reg16_DE: begin
-                                                       registers[`REG_D] <= tmp;
-                                                       registers[`REG_E] <= tmp2;
-                                               end
-                                               `INSN_reg16_HL: begin
-                                                       registers[`REG_H] <= tmp;
-                                                       registers[`REG_L] <= tmp2;
-                                               end
-                                               `INSN_reg16_SP: begin
-                                                       registers[`REG_SPH] <= tmp;
-                                                       registers[`REG_SPL] <= tmp2;
-                                               end
-                                               endcase
-                                       end
-                               endcase
-                       end
-                       `INSN_VOP_INTR: begin
-                               case (cycle)
-                               0:      begin end
-                               1:      begin end
-                               2:      begin
-                                               ie <= 0;
-                                               {registers[`REG_PCH],registers[`REG_PCL]} <=
-                                                       {8'b0,jaddr};
-                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                                       {registers[`REG_SPH],registers[`REG_SPL]} - 2;
-                                       end
-                               endcase
-                       end
-                       `INSN_DI: ie <= 0;
-                       `INSN_EI: iedelay <= 1;

                        default:
                                $stop;
                        endcase
                        default:
                                $stop;
                        endcase