Set up the bus a little before the clock.
[fpgaboy.git] / insn_ldx_ahl.v
index a16d6ba..a2d2420 100644 (file)
@@ -1,18 +1,13 @@
 `ifdef EXECUTE
        `INSN_LDx_AHL: begin
                case (cycle)
-               0:      begin
-                               address <= {registers[`REG_H],registers[`REG_L]};
-                               if (opcode[3]) begin    // LDx A, (HL)
-                                       rd <= 1;
-                               end else begin
-                                       wr <= 1;
-                                       wdata <= registers[`REG_A];
-                               end
-                       end
+               0:      if (opcode[3])          // LDx A, (HL)
+                               `EXEC_READ(`_HL)
+                       else
+                               `EXEC_WRITE(`_HL, `_A)
                1:      begin
-                               `EXEC_NEWCYCLE;
-                               `EXEC_INC_PC;
+                               `EXEC_NEWCYCLE
+                               `EXEC_INC_PC
                        end
                endcase
        end
                0:      begin /* Type F */ end
                1:      begin
                                if (opcode[3])
-                                       registers[`REG_A] <= rdata;
-                               {registers[`REG_H],registers[`REG_L]} <=
-                                       opcode[4] ? // if set, LDD, else LDI
-                                       ({registers[`REG_H],registers[`REG_L]} - 1) :
-                                       ({registers[`REG_H],registers[`REG_L]} + 1);
+                                       `_A <= rdata;
+                               `_HL <= opcode[4] ? // if set, LDD, else LDI
+                                       (`_HL - 1) :
+                                       (`_HL + 1);
                        end
                endcase
        end
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