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[fpgaboy.git] / insn_alu8.v
index 8470e27..b6d4c63 100644 (file)
@@ -1,20 +1,21 @@
 `ifdef EXECUTE
-       `INSN_ALU8: begin
-               if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
-                       // fffffffff fuck your shit, read from (HL) :(
-                       rd <= 1;
-                       address <= {registers[`REG_H], registers[`REG_L]};
-               end else begin
-                       `EXEC_NEWCYCLE;
-                       `EXEC_INC_PC;
+       `INSN_ALU8,`INSN_ALU8IMM: begin
+               if ((opcode[7:6] == 2'b11) && (cycle == 0)) begin       // alu8imm
+                       `EXEC_INC_PC
+                       `EXEC_READ(`_PC + 1)
+               end else if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0))
+                       `EXEC_READ(`_HL)
+               else begin
+                       `EXEC_NEWCYCLE
+                       `EXEC_INC_PC
                        case (opcode[2:0])
-                       `INSN_reg_A:    tmp <= registers[`REG_A];
-                       `INSN_reg_B:    tmp <= registers[`REG_B];
-                       `INSN_reg_C:    tmp <= registers[`REG_C];
-                       `INSN_reg_D:    tmp <= registers[`REG_D];
-                       `INSN_reg_E:    tmp <= registers[`REG_E];
-                       `INSN_reg_H:    tmp <= registers[`REG_H];
-                       `INSN_reg_L:    tmp <= registers[`REG_L];
+                       `INSN_reg_A:    tmp <= `_A;
+                       `INSN_reg_B:    tmp <= `_B;
+                       `INSN_reg_C:    tmp <= `_C;
+                       `INSN_reg_D:    tmp <= `_D;
+                       `INSN_reg_E:    tmp <= `_E;
+                       `INSN_reg_H:    tmp <= `_H;
+                       `INSN_reg_L:    tmp <= `_L;
                        `INSN_reg_dHL:  tmp <= rdata;
                        endcase
                end
 `endif
 
 `ifdef WRITEBACK
-       `INSN_ALU8: begin
-               if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
+       `INSN_ALU8,`INSN_ALU8IMM: begin
+               if (((opcode[2:0] == `INSN_reg_dHL) || (opcode[7:6] == 2'b11)) && (cycle == 0)) begin
                        /* Sit on our asses. */
                end else begin          /* Actually do the computation! */
                        case (opcode[5:3])
                        `INSN_alu_ADD: begin
-                               registers[`REG_A] <=
-                                       registers[`REG_A] + tmp;
-                               registers[`REG_F] <=
-                                       { /* Z */ ((registers[`REG_A] + tmp) == 0) ? 1'b1 : 1'b0,
+                               `_A <= `_A + tmp;
+                               `_F <=  { /* Z */ ((`_A + tmp) == 0) ? 1'b1 : 1'b0,
                                          /* N */ 1'b0,
-                                         /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
-                                         /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
-                                         registers[`REG_F][3:0]
+                                         /* H */ (({1'b0,`_A[3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+                                         /* C */ (({1'b0,`_A} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+                                         `_F[3:0]
                                        };
                        end
                        `INSN_alu_ADC: begin
-                               registers[`REG_A] <=
-                                       registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]};
-                               registers[`REG_F] <=
-                                       { /* Z */ ((registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]}) == 0) ? 1'b1 : 1'b0,
+                               `_A <= `_A + tmp + {7'b0,`_F[4]};
+                               `_F <=  { /* Z */ ((`_A + tmp + {7'b0,`_F[4]}) == 0) ? 1'b1 : 1'b0,
                                          /* N */ 1'b0,
-                                         /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]}) >> 4 == 1) ? 1'b1 : 1'b0,
-                                         /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp} + {8'b0,registers[`REG_F][4]}) >> 8 == 1) ? 1'b1 : 1'b0,
-                                         registers[`REG_F][3:0]
+                                         /* H */ (({1'b0,`_A[3:0]} + {1'b0,tmp[3:0]} + {4'b0,`_F[4]}) >> 4 == 1) ? 1'b1 : 1'b0,
+                                         /* C */ (({1'b0,`_A} + {1'b0,tmp} + {8'b0,`_F[4]}) >> 8 == 1) ? 1'b1 : 1'b0,
+                                         `_F[3:0]
                                        };
                        end
                        `INSN_alu_SUB: begin
-                               registers[`REG_A] <=
-                                       registers[`REG_A] - tmp;
-                               registers[`REG_F] <=
-                                       { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+                               `_A <= `_A - tmp;
+                               `_F <=  { /* Z */ (`_A == tmp) ? 1'b1 : 1'b0,
                                          /* N */ 1'b1,
-                                         /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
-                                         /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
-                                         registers[`REG_F][3:0]
+                                         /* H */ (tmp[3:0] > `_A[3:0]) ? 1'b1 : 1'b0,
+                                         /* C */ (tmp > `_A) ? 1'b1 : 1'b0,
+                                         `_F[3:0]
                                        };
                        end
                        `INSN_alu_SBC: begin
-                               registers[`REG_A] <=
-                                       registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]});
-                               registers[`REG_F] <=
-                                       { /* Z */ ((registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]})) == 0) ? 1'b1 : 1'b0,
+                               `_A <= `_A - (tmp + {7'b0,`_F[4]});
+                               `_F <=  { /* Z */ ((`_A - (tmp + {7'b0,`_F[4]})) == 0) ? 1'b1 : 1'b0,
                                          /* N */ 1'b1,
-                                         /* H */ (({1'b0,registers[`REG_A][3:0]} - ({1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]})) >> 4 == 1) ? 1'b1 : 1'b0,
-                                         /* C */ (({1'b0,registers[`REG_A]} - ({1'b0,tmp} + {8'b0,registers[`REG_F][4]})) >> 8 == 1) ? 1'b1 : 1'b0,
-                                         registers[`REG_F][3:0]
+                                         /* H */ (({1'b0,tmp[3:0]} + {4'b0,`_F[4]}) > {1'b0,`_A[3:0]}) ? 1'b1 : 1'b0,
+                                         /* C */ (({1'b0,tmp} + {8'b0,`_F[4]}) > {1'b0,`_A[7:0]}) ? 1'b1 : 1'b0,
+                                         `_F[3:0]
                                        };
                        end
                        `INSN_alu_AND: begin
-                               registers[`REG_A] <=
-                                       registers[`REG_A] & tmp;
-                               registers[`REG_F] <=
-                                       { /* Z */ ((registers[`REG_A] & tmp) == 0) ? 1'b1 : 1'b0,
+                               `_A <= `_A & tmp;
+                               `_F <=  { /* Z */ ((`_A & tmp) == 0) ? 1'b1 : 1'b0,
                                          3'b010,
-                                         registers[`REG_F][3:0]
+                                         `_F[3:0]
                                        };
                        end
                        `INSN_alu_OR: begin
-                               registers[`REG_A] <=
-                                       registers[`REG_A] | tmp;
-                               registers[`REG_F] <=
-                                       { /* Z */ ((registers[`REG_A] | tmp) == 0) ? 1'b1 : 1'b0,
+                               `_A <= `_A | tmp;
+                               `_F <=  { /* Z */ ((`_A | tmp) == 0) ? 1'b1 : 1'b0,
                                          3'b000,
-                                         registers[`REG_F][3:0]
+                                         `_F[3:0]
                                        };
                        end
                        `INSN_alu_XOR: begin
-                               registers[`REG_A] <=
-                                       registers[`REG_A] ^ tmp;
-                               registers[`REG_F] <=
-                                       { /* Z */ ((registers[`REG_A] ^ tmp) == 0) ? 1'b1 : 1'b0,
+                               `_A <= `_A ^ tmp;
+                               `_F <=  { /* Z */ ((`_A ^ tmp) == 0) ? 1'b1 : 1'b0,
                                          3'b000,
-                                         registers[`REG_F][3:0]
+                                         `_F[3:0]
                                        };
                        end
                        `INSN_alu_CP: begin
-                               registers[`REG_F] <=
-                                       { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+                               `_F <=  { /* Z */ (`_A == tmp) ? 1'b1 : 1'b0,
                                          /* N */ 1'b1,
-                                         /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
-                                         /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
-                                         registers[`REG_F][3:0]
+                                         /* H */ (tmp[3:0] > `_A[3:0]) ? 1'b1 : 1'b0,
+                                         /* C */ (tmp > `_A) ? 1'b1 : 1'b0,
+                                         `_F[3:0]
                                        };
                        end
                        default:
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