Rework it all to use the new macros.

[fpgaboy.git] / insn_alu_a.v

diff --git a/insn_alu_a.v b/insn_alu_a.v
index fe3315af76c971ad7e09f36084e2a64791f60990..57a74fc9d71cb6f4c488251db7810f642583afde 100644 (file)
--- a/insn_alu_a.v
+++ b/insn_alu_a.v
@@ -1,7 +1,7 @@
 `ifdef EXECUTE
        `INSN_ALU_A: begin
-               `EXEC_NEWCYCLE;
-               `EXEC_INC_PC;
+               `EXEC_NEWCYCLE
+               `EXEC_INC_PC
        end
 `endif
 
@@ -9,30 +9,30 @@
        `INSN_ALU_A: begin
                case(opcode[5:3])
                `INSN_alu_RLCA: begin
-                       registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_A][7]};
-                       registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
+                       `_A <= {`_A[6:0],`_A[7]};
+                       `_F <= {`_F[7:5],`_A[7],`_F[3:0]};
                end
                `INSN_alu_RRCA: begin
-                       registers[`REG_A] <= {registers[`REG_A][0],registers[`REG_A][7:1]};
-                       registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
+                       `_A <= {`_A[0],`_A[7:1]};
+                       `_F <= {`_F[7:5],`_A[0],`_F[3:0]};
                end
                `INSN_alu_RLA: begin
-                       registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_F][4]};
-                       registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
+                       `_A <= {`_A[6:0],`_F[4]};
+                       `_F <= {`_F[7:5],`_A[7],`_F[3:0]};
                end
                `INSN_alu_RRA: begin
-                       registers[`REG_A] <= {registers[`REG_A][4],registers[`REG_A][7:1]};
-                       registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
+                       `_A <= {`_A[4],`_A[7:1]};
+                       `_F <= {`_F[7:5],`_A[0],`_F[3:0]};
                end
                `INSN_alu_CPL: begin
-                       registers[`REG_A] <= ~registers[`REG_A];
-                       registers[`REG_F] <= {registers[`REG_F][7],1'b1,1'b1,registers[`REG_F][4:0]};
+                       `_A <= ~`_A;
+                       `_F <= {`_F[7],1'b1,1'b1,`_F[4:0]};
                end
                `INSN_alu_SCF: begin
-                       registers[`REG_F] <= {registers[`REG_F][7:5],1'b1,registers[`REG_F][3:0]};
+                       `_F <= {`_F[7:5],1'b1,`_F[3:0]};
                end
                `INSN_alu_CCF: begin
-                       registers[`REG_F] <= {registers[`REG_F][7:5],~registers[`REG_F][4],registers[`REG_F][3:0]};
+                       `_F <= {`_F[7:5],~`_F[4],`_F[3:0]};
                end
                endcase
        end