Move macro defines out to files

[fpgaboy.git] / LCDC.v

diff --git a/LCDC.v b/LCDC.v
index 8f237eb1aae11a5e11271ec28b00a52dfc3143ab..cb204d5df1e5c6b58b0761cd4474c099f6abf946 100644 (file)
--- a/LCDC.v
+++ b/LCDC.v
@@ -19,7 +19,11 @@ module LCDC(
        output wire lcdcirq,
        output wire vblankirq,
        output wire lcdclk, lcdvs, lcdhs,
        output wire lcdcirq,
        output wire vblankirq,
        output wire lcdclk, lcdvs, lcdhs,

-       output wire [2:0] lcdr, lcdg, output wire [1:0] lcdb);
+       output reg [2:0] lcdr, lcdg, output reg [1:0] lcdb);
+       
+       /***** Bus latches *****/
+       reg rdlatch = 0;
+       reg [15:0] addrlatch = 0;

        
        /***** Needed prototypes *****/
        wire [1:0] pixdata;
        
        /***** Needed prototypes *****/
        wire [1:0] pixdata;


@@ -27,11 +31,10 @@ module LCDC(
        /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
        reg clk4 = 0;
        always @(posedge clk)
        /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
        reg clk4 = 0;
        always @(posedge clk)

-               clk4 = ~clk4;
-       assign lcdclk = clk4;
+               clk4 <= ~clk4;

        
        /***** LCD control registers *****/
        
        /***** LCD control registers *****/

-       reg [7:0] rLCDC = 8'h91;
+       reg [7:0] rLCDC = 8'h00;

        reg [7:0] rSTAT = 8'h00;
        reg [7:0] rSCY = 8'b00;
        reg [7:0] rSCX = 8'b00;
        reg [7:0] rSTAT = 8'h00;
        reg [7:0] rSCY = 8'b00;
        reg [7:0] rSCX = 8'b00;


@@ -63,8 +66,8 @@ module LCDC(
        reg [8:0] posx = 9'h000;
        reg [7:0] posy = 8'h00;
        
        reg [8:0] posx = 9'h000;
        reg [7:0] posy = 8'h00;
        

-       wire vraminuse = (posx < 163);
-       wire oaminuse = (posx > 369);
+       wire vraminuse = (posx < 163) && (posy < 144) && rLCDC[7];
+       wire oaminuse = (posx > 369) && (posy < 144) && rLCDC[7];

        
        wire display = (posx > 2) && (posx < 163) && (posy < 144);
        
        
        wire display = (posx > 2) && (posx < 163) && (posy < 144);
        


@@ -74,11 +77,16 @@ module LCDC(
                                 2'b00)
                                : 2'b01;
        
                                 2'b00)
                                : 2'b01;
        

-       assign lcdvs = (posy == 153) && (posx == 455);
-       assign lcdhs = (posx == 455);
-       assign lcdr = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000;
-       assign lcdg = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000;
-       assign lcdb = display ? {posy < rSCY ? 2'b11 : 2'b00} : 2'b00;
+       wire [7:0] vxpos = rSCX + posx - 3;
+       wire [7:0] vypos = rSCY + posy;
+       
+       assign lcdvs = (posy == 153) && (posx == 2) && rLCDC[7];
+       assign lcdhs = (posx == 2) && rLCDC[7];
+       assign lcdclk = clk4;
+       
+       wire [2:0] lcdr_ = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000;
+       wire [2:0] lcdg_ = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000;
+       wire [1:0] lcdb_ = display ? {(vypos < 8 || vxpos < 8) ? 2'b11 : 2'b00} : 2'b00;

        
        reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;
        assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);
        
        reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;
        assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);


@@ -115,6 +123,10 @@ module LCDC(
                        end
                        lycirq <= 0;
                end
                        end
                        lycirq <= 0;
                end

+               
+               lcdr <= lcdr_;
+               lcdg <= lcdg_;
+               lcdb <= lcdb_;

        end
        
        /***** Video RAM *****/
        end
        
        /***** Video RAM *****/


@@ -123,69 +135,69 @@ module LCDC(
         * Tile data from 8000-8FFF or 8800-97FF
         * Background tile maps 9800-9BFF or 9C00-9FFF
         */
         * Tile data from 8000-8FFF or 8800-97FF
         * Background tile maps 9800-9BFF or 9C00-9FFF
         */

-       reg [7:0] tiledata [6143:0];
+       reg [7:0] tiledatahigh [3071:0];
+       reg [7:0] tiledatalow [3071:0];

        reg [7:0] bgmap1 [1023:0];
        reg [7:0] bgmap2 [1023:0];
        
        // Upper five bits are Y coord, lower five bits are X coord
        reg [7:0] bgmap1 [1023:0];
        reg [7:0] bgmap2 [1023:0];
        
        // Upper five bits are Y coord, lower five bits are X coord

-       wire [7:0] vxpos = rSCX + posx - 3;
-       wire [7:0] vypos = rSCY + posy;
-       
-       // The new tile number is loaded when vxpos[2:0] is 3'b101
-       // The new tile data low is loaded when vxpos[2:0] is 3'b110
-       // The new tile data high is loaded when vxpos[2:0] is 3'b111
+       // The new tile number is loaded when vxpos[2:0] is 3'b110
+       // The new tile data is loaded when vxpos[2:0] is 3'b111

        // The new tile data is latched and ready when vxpos[2:0] is 3'b000!
        // The new tile data is latched and ready when vxpos[2:0] is 3'b000!

-       wire [9:0] bgmapaddr = {vypos[7:3], vxpos[7:3]};
+       wire [7:0] vxpos_ = vxpos + 1;
+       wire [9:0] bgmapaddr = {vypos[7:3], vxpos_[7:3]};

        reg [7:0] tileno;
        reg [7:0] tileno;

-       wire [10:0] tileaddr = {tileno, vypos[2:1]};
-       reg [7:0] tilelowtmp, tilehigh, tilelow;
-       assign pixdata = {tilehigh[vxpos[2:0]], tilelow[vxpos[2:0]]};
+       wire [10:0] tileaddr = {tileno, vypos[2:0]};
+       reg [7:0] tilehigh, tilelow;
+       wire [1:0] prepal = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]};
+       assign pixdata = 2'b11-{rBGP[{prepal,1'b1}],rBGP[{prepal,1'b0}]};

        
        wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF);
        wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF);
        
        wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF);
        wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF);

+
+       wire [9:0] bgmapaddr_in = vraminuse ? bgmapaddr : addr[9:0];
+       wire [11:0] tileaddr_in = vraminuse ? tileaddr : addr[12:1];

        
        

-       always @(negedge clk)
-               if (vraminuse) begin
-                       if ((posx == 0) || ((posx > 2) && (vxpos[2:0] == 3'b101)))
-                               tileno <= bgmap1[bgmapaddr];
-                       else if ((posx == 1) || ((posx > 2) && (vxpos[2:0] == 3'b110)))
-                               tilelowtmp <= tiledata[{tileaddr, 1'b0}];
-                       else if ((posx == 2) || ((posx > 2) && (vxpos[2:0] == 3'b111))) begin
-                               tilehigh <= tiledata[{tileaddr, 1'b1}];
-                               tilelow <= tilelowtmp;
-                       end
-               end else begin
-                       if (decode_tiledata) begin
-                               tilelowtmp <= tiledata[addr[12:0]];
-                               if (wr)
-                                       tiledata[addr[12:0]] <= data;
-                       end else if (decode_bgmap1) begin
-                               tileno <= bgmap1[addr[12:0]];
-                               if (wr)
-                                       bgmap1[addr[12:0]] <= data;
-                       end
+       always @(posedge clk)
+       begin
+               if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_bgmap1) begin
+                       tileno <= bgmap1[bgmapaddr_in];
+                       if (wr && decode_bgmap1 && ~vraminuse)
+                               bgmap1[bgmapaddr_in] <= data;
+               end
+               if ((vraminuse && ((posx == 3) || (vxpos[2:0] == 3'b000))) || decode_tiledata) begin
+                       tilehigh <= tiledatahigh[tileaddr_in];
+                       tilelow <= tiledatalow[tileaddr_in];
+                       if (wr && addr[0] && decode_tiledata && ~vraminuse)
+                               tiledatahigh[tileaddr_in] <= data;
+                       if (wr && ~addr[0] && decode_tiledata && ~vraminuse)
+                               tiledatalow[tileaddr_in] <= data;

                end
                end

+       end

   
        /***** Bus interface *****/
   
        /***** Bus interface *****/

-       assign data = rd ?
-                       (addr == `ADDR_LCDC) ? rLCDC :
-                       (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
-                       (addr == `ADDR_SCY) ? rSCY :
-                       (addr == `ADDR_SCX) ? rSCX :
-                       (addr == `ADDR_LY) ? posy :
-                       (addr == `ADDR_LYC) ? rLYC :
-                       (addr == `ADDR_BGP) ? rBGP :
-                       (addr == `ADDR_OBP0) ? rOBP0 :
-                       (addr == `ADDR_OBP1) ? rOBP1 :
-                       (addr == `ADDR_WY) ? rWY :
-                       (addr == `ADDR_WX) ? rWX :
-                       (decode_tiledata) ? tilelowtmp :
-                       (decode_bgmap1) ? tileno :
-                       8'bzzzzzzzz :
+       assign data = rdlatch ?
+                       ((addrlatch == `ADDR_LCDC) ? rLCDC :
+                        (addrlatch == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
+                        (addrlatch == `ADDR_SCY) ? rSCY :
+                        (addrlatch == `ADDR_SCX) ? rSCX :
+                        (addrlatch == `ADDR_LY) ? posy :
+                        (addrlatch == `ADDR_LYC) ? rLYC :
+                        (addrlatch == `ADDR_BGP) ? rBGP :
+                        (addrlatch == `ADDR_OBP0) ? rOBP0 :
+                        (addrlatch == `ADDR_OBP1) ? rOBP1 :
+                        (addrlatch == `ADDR_WY) ? rWY :
+                        (addrlatch == `ADDR_WX) ? rWX :
+                        (decode_tiledata && addrlatch[0]) ? tilehigh :
+                        (decode_tiledata && ~addrlatch[0]) ? tilelow :
+                        (decode_bgmap1) ? tileno :
+                        8'bzzzzzzzz) :

                8'bzzzzzzzz;
   
                8'bzzzzzzzz;
   

-       always @(negedge clk)
+       always @(posedge clk)

        begin
        begin

+               rdlatch <= rd;
+               addrlatch <= addr;

                if (wr)
                        case (addr)
                        `ADDR_LCDC:     rLCDC <= data;
                if (wr)
                        case (addr)
                        `ADDR_LCDC:     rLCDC <= data;