Cut 1 at interrupt support for CPU

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 8b8d61344f712e4c39cfae009bf71969f67039a9..7319ebf6aceb8cc2f7b7f72a3f0877bb93a39aaa 100644 (file)
--- a/System.v
+++ b/System.v
@@ -76,13 +76,18 @@ module CoreTop(
        wire [15:0] addr;       
        wire [7:0] data;
        wire wr, rd;
+       
+       wire irq, tmrirq;
+       wire [7:0] jaddr;
 
        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),
                .busdata(data),
                .buswr(wr),
-               .busrd(rd));
+               .busrd(rd),
+               .irq(irq),
+               .jaddr(jaddr));
        
        ROM rom(
                .address(addr),
@@ -125,8 +130,6 @@ module CoreTop(
                .wr(wr),
                .rd(rd));
 
-       wire irq, tmrirq;
-       wire [7:0] jaddr;
        Timer tmr(
                .clk(clk),
                .wr(wr),
@@ -156,6 +159,9 @@ module TestBench();
        wire [7:0] data;
        wire wr, rd;
        
+       wire irq, tmrirq;
+       wire [7:0] jaddr;
+       
 //     wire [7:0] leds;
 //     wire [7:0] switches;
        
@@ -165,7 +171,9 @@ module TestBench();
                .busaddress(addr),
                .busdata(data),
                .buswr(wr),
-               .busrd(rd));
+               .busrd(rd),
+               .irq(irq),
+               .jaddr(jaddr));
        
        ROM rom(
                .clk(clk),
@@ -190,8 +198,6 @@ module TestBench();
                .rd(rd),
                .serial(serio));
        
-       wire irq, tmrirq;
-       wire [7:0] jaddr;
        Timer tmr(
                .clk(clk),
                .wr(wr),