+ `INSN_VOP_INTR: begin
+ case (cycle)
+ 0: begin end
+ 1: {registers[`REG_SPH],registers[`REG_SPL]}
+ <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+ 2: begin
+ ie <= 0;
+ {registers[`REG_PCH],registers[`REG_PCL]} <=
+ {8'b0,jaddr};
+ end
+ endcase
+ end
+ `INSN_DI: ie <= 0;
+ `INSN_EI: iedelay <= 1;