Fix some simulator-only bugs involving debugging/illegal states. Make rd and wr...

[fpgaboy.git] / opcodes

diff --git a/opcodes b/opcodes
index 5a03850e40b95c2eb790e0ee96493375d59b714b..09f68fbce78aa2756211461a9e610ad3ede999ba 100644 (file)
--- a/opcodes
+++ b/opcodes
@@ -95,15 +95,6 @@ bits                   insn               notes
 1100 1011 0011 0110    SWAP  (HL)
 1100 1011 0011 0111    SWAP  A
 
 1100 1011 0011 0110    SWAP  (HL)
 1100 1011 0011 0111    SWAP  A
 

-1100 1011 0100 0000    BIT   imm3, B      test bit specified by imm3
-1100 1011 0100 0001    BIT   imm3, C
-1100 1011 0100 0010    BIT   imm3, D
-1100 1011 0100 0011    BIT   imm3, E
-1100 1011 0100 0100    BIT   imm3, H
-1100 1011 0100 0101    BIT   imm3, L
-1100 1011 0100 0110    BIT   imm3, (HL)
-1100 1011 0100 0111    BIT   imm3, A
-

 1100 1011 1000 0000    RES   imm3, B      reset bit specified by imm3
 1100 1011 1000 0001    RES   imm3, C
 1100 1011 1000 0010    RES   imm3, D
 1100 1011 1000 0000    RES   imm3, B      reset bit specified by imm3
 1100 1011 1000 0001    RES   imm3, C
 1100 1011 1000 0010    RES   imm3, D