]> Joshua Wise's Git repositories - fpgaboy.git/blobdiff - GBZ80Core.v
Our first ALU operation -- ADD
[fpgaboy.git] / GBZ80Core.v
index 9bc60a8bfd2dc67da31b34438ad779e893103f5c..0cdefa546c112fb204503bc5e17a6848e9136639 100644 (file)
 `define STATE_WRITEBACK                2'h3
 
 `define INSN_LD_reg_imm8       8'b00xxx110
-`define INSN_imm8_reg_A                3'b111
-`define INSN_imm8_reg_B                3'b000
-`define INSN_imm8_reg_C                3'b001
-`define INSN_imm8_reg_D                3'b010
-`define INSN_imm8_reg_E                3'b011
-`define INSN_imm8_reg_H                3'b100
-`define INSN_imm8_reg_L                3'b101
-`define INSN_imm8_reg_dHL      3'b110
+`define INSN_HALT                              8'b01110110
+`define INSN_LD_HL_reg         8'b01110xxx
+`define INSN_LD_reg_HL         8'b01xxx110
+`define INSN_LD_reg_reg                8'b01xxxxxx
+`define INSN_LD_reg_imm16      8'b00xx0001
+`define INSN_LD_SP_HL          8'b11111001
+`define INSN_PUSH_reg          8'b11xx0101
+`define INSN_POP_reg                   8'b11xx0001
+`define INSN_LDH_AC                    8'b111x0010     // Either LDH A,(C) or LDH (C),A
+`define INSN_LDx_AHL                   8'b001xx010     // LDD/LDI A,(HL) / (HL),A
+`define INSN_ALU8                              8'b10xxxxxx     // 10 xxx yyy
+
+`define INSN_reg_A             3'b111
+`define INSN_reg_B             3'b000
+`define INSN_reg_C             3'b001
+`define INSN_reg_D             3'b010
+`define INSN_reg_E             3'b011
+`define INSN_reg_H             3'b100
+`define INSN_reg_L             3'b101
+`define INSN_reg_dHL   3'b110
+`define INSN_reg16_BC  2'b00
+`define INSN_reg16_DE  2'b01
+`define INSN_reg16_HL  2'b10
+`define INSN_reg16_SP  2'b11
+`define INSN_stack_AF  2'b11
+`define INSN_stack_BC  2'b00
+`define INSN_stack_DE  2'b01
+`define INSN_stack_HL  2'b10
+`define INSN_alu_ADD           3'b000
+`define INSN_alu_ADC           3'b001
+`define INSN_alu_SUB           3'b010
+`define INSN_alu_SBC           3'b011
+`define INSN_alu_AND           3'b100
+`define INSN_alu_XOR           3'b101
+`define INSN_alu_OR            3'b110
+`define INSN_alu_CP            3'b111          // Oh lawd, is dat some CP?
 
 module GBZ80Core(
        input clk,
@@ -49,22 +77,24 @@ module GBZ80Core(
        reg [7:0] rdata, wdata;         /* Read data from this bus cycle, or write data for the next. */
        reg rd = 1, wr = 0, newcycle = 1;
        
+       reg [7:0] tmp;                                  /* Generic temporary reg. */
+       
        reg [7:0] buswdata;
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
        
        initial begin
-               registers[ 0] = 0;
-               registers[ 1] = 0;
-               registers[ 2] = 0;
-               registers[ 3] = 0;
-               registers[ 4] = 0;
-               registers[ 5] = 0;
-               registers[ 6] = 0;
-               registers[ 7] = 0;
-               registers[ 8] = 0;
-               registers[ 9] = 0;
-               registers[10] = 0;
-               registers[11] = 0;
+               registers[ 0] <= 0;
+               registers[ 1] <= 0;
+               registers[ 2] <= 0;
+               registers[ 3] <= 0;
+               registers[ 4] <= 0;
+               registers[ 5] <= 0;
+               registers[ 6] <= 0;
+               registers[ 7] <= 0;
+               registers[ 8] <= 0;
+               registers[ 9] <= 0;
+               registers[10] <= 0;
+               registers[11] <= 0;
        end
 
        always @(posedge clk)
@@ -84,11 +114,16 @@ module GBZ80Core(
                        if (newcycle) begin
                                opcode <= busdata;
                                rdata <= busdata;
+                               newcycle <= 0;
                                cycle <= 0;
                        end else
                                if (rd) rdata <= busdata;
                        buswr <= 0;
                        busrd <= 0;
+                       wr <= 0;
+                       rd <= 0;
+                       address <= 16'bxxxxxxxxxxxxxxxx;        // Make it obvious if something of type has happened.
+                       wdata <= 8'bxxxxxxxx;
                        state <= `STATE_EXECUTE;
                end
                `STATE_EXECUTE: begin
@@ -104,12 +139,11 @@ module GBZ80Core(
                                0:      begin
                                                `EXEC_INC_PC;
                                                `EXEC_NEXTADDR_PCINC;
-                                               newcycle <= 0;
                                                rd <= 1;
                                        end
                                1: begin
                                                `EXEC_INC_PC;
-                                               if (opcode[5:3] == `INSN_imm8_reg_dHL) begin
+                                               if (opcode[5:3] == `INSN_reg_dHL) begin
                                                        address <= {registers[`REG_H], registers[`REG_L]};
                                                        wdata <= rdata;
                                                        rd <= 0;
@@ -123,26 +157,368 @@ module GBZ80Core(
                                        end
                                endcase
                        end
+                       `INSN_HALT: begin
+                               `EXEC_NEWCYCLE;
+                               /* XXX Interrupts needed for HALT. */
+                       end
+                       `INSN_LD_HL_reg: begin
+                               case (cycle)
+                               0:      begin
+                                               case (opcode[2:0])
+                                               `INSN_reg_A:    begin wdata <= registers[`REG_A]; end
+                                               `INSN_reg_B:    begin wdata <= registers[`REG_B]; end
+                                               `INSN_reg_C:    begin wdata <= registers[`REG_C]; end
+                                               `INSN_reg_D:    begin wdata <= registers[`REG_D]; end
+                                               `INSN_reg_E:    begin wdata <= registers[`REG_E]; end
+                                               `INSN_reg_H:    begin wdata <= registers[`REG_H]; end
+                                               `INSN_reg_L:    begin wdata <= registers[`REG_L]; end
+                                               endcase
+                                               address <= {registers[`REG_H], registers[`REG_L]};
+                                               wr <= 1; rd <= 0;
+                                       end
+                               1:      begin
+                                               `EXEC_INC_PC;
+                                               `EXEC_NEWCYCLE;
+                                       end
+                               endcase
+                       end
+                       `INSN_LD_reg_HL: begin
+                               case(cycle)
+                               0: begin
+                                               address <= {registers[`REG_H], registers[`REG_L]};
+                                               rd <= 1;
+                                       end
+                               1: begin
+                                               tmp <= rdata;
+                                               `EXEC_INC_PC;
+                                               `EXEC_NEWCYCLE;
+                                       end
+                               endcase
+                       end
+                       `INSN_LD_reg_reg: begin
+                               `EXEC_INC_PC;
+                               `EXEC_NEWCYCLE;
+                               case (opcode[2:0])
+                               `INSN_reg_A:    begin tmp <= registers[`REG_A]; end
+                               `INSN_reg_B:    begin tmp <= registers[`REG_B]; end
+                               `INSN_reg_C:    begin tmp <= registers[`REG_C]; end
+                               `INSN_reg_D:    begin tmp <= registers[`REG_D]; end
+                               `INSN_reg_E:    begin tmp <= registers[`REG_E]; end
+                               `INSN_reg_H:    begin tmp <= registers[`REG_H]; end
+                               `INSN_reg_L:    begin tmp <= registers[`REG_L]; end
+                               endcase
+                       end
+                       `INSN_LD_reg_imm16: begin
+                               `EXEC_INC_PC;
+                               case (cycle)
+                               0:      begin
+                                               `EXEC_NEXTADDR_PCINC;
+                                               rd <= 1;
+                                       end
+                               1:      begin
+                                               `EXEC_NEXTADDR_PCINC;
+                                               rd <= 1;
+                                       end
+                               2: begin `EXEC_NEWCYCLE; end
+                               endcase
+                       end
+                       `INSN_LD_SP_HL: begin
+                               case (cycle)
+                               0:      begin
+                                               tmp <= registers[`REG_H];
+                                       end
+                               1:      begin
+                                               `EXEC_NEWCYCLE;
+                                               `EXEC_INC_PC;
+                                               tmp <= registers[`REG_L];
+                                       end
+                               endcase
+                       end
+                       `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
+                               case (cycle)
+                               0: begin
+                                               wr <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+                                               case (opcode[5:4])
+                                               `INSN_stack_AF: wdata <= registers[`REG_A];
+                                               `INSN_stack_BC: wdata <= registers[`REG_B];
+                                               `INSN_stack_DE: wdata <= registers[`REG_D];
+                                               `INSN_stack_HL: wdata <= registers[`REG_H];
+                                               endcase
+                                       end
+                               1: begin
+                                               wr <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+                                               case (opcode[5:4])
+                                               `INSN_stack_AF: wdata <= registers[`REG_F];
+                                               `INSN_stack_BC: wdata <= registers[`REG_C];
+                                               `INSN_stack_DE: wdata <= registers[`REG_E];
+                                               `INSN_stack_HL: wdata <= registers[`REG_L];
+                                               endcase
+                                       end
+                               2:      begin /* TWIDDLE OUR FUCKING THUMBS! */ end
+                               3: begin
+                                               `EXEC_NEWCYCLE;
+                                               `EXEC_INC_PC;
+                                       end
+                               endcase
+                       end
+                       `INSN_POP_reg: begin    /* POP is 12 cycles! */
+                               case (cycle)
+                               0: begin
+                                               rd <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
+                                       end
+                               1: begin
+                                               rd <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
+                                       end
+                               2: begin
+                                               `EXEC_NEWCYCLE;
+                                               `EXEC_INC_PC;
+                                       end
+                               endcase
+                       end
+                       `INSN_LDH_AC: begin
+                               case (cycle)
+                               0:      begin
+                                               address <= {8'hFF,registers[`REG_C]};
+                                               if (opcode[4]) begin    // LD A,(C)
+                                                       rd <= 1;
+                                               end else begin
+                                                       wr <= 1;
+                                                       wdata <= registers[`REG_A];
+                                               end
+                                       end
+                               1: begin
+                                               `EXEC_NEWCYCLE;
+                                               `EXEC_INC_PC;
+                                       end
+                               endcase
+                       end
+                       `INSN_LDx_AHL: begin
+                               case (cycle)
+                               0: begin
+                                               address <= {registers[`REG_H],registers[`REG_L]};
+                                               if (opcode[3]) begin    // LDx A, (HL)
+                                                       rd <= 1;
+                                               end else begin
+                                                       wr <= 1;
+                                                       wdata <= registers[`REG_A];
+                                               end
+                                       end
+                               1:      begin
+                                               `EXEC_NEWCYCLE;
+                                               `EXEC_INC_PC;
+                                       end
+                               endcase
+                       end
+                       `INSN_ALU8: begin
+                               if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
+                                       // fffffffff fuck your shit, read from (HL) :(
+                                       rd <= 1;
+                                       address <= {registers[`REG_H], registers[`REG_L]};
+                               end else begin
+                                       `EXEC_NEWCYCLE;
+                                       `EXEC_INC_PC;
+                                       case (opcode[2:0])
+                                       `INSN_reg_A:    begin tmp <= registers[`REG_A]; end
+                                       `INSN_reg_B:    begin tmp <= registers[`REG_B]; end
+                                       `INSN_reg_C:    begin tmp <= registers[`REG_C]; end
+                                       `INSN_reg_D:    begin tmp <= registers[`REG_D]; end
+                                       `INSN_reg_E:    begin tmp <= registers[`REG_E]; end
+                                       `INSN_reg_H:    begin tmp <= registers[`REG_H]; end
+                                       `INSN_reg_L:    begin tmp <= registers[`REG_L]; end
+                                       `INSN_reg_dHL:  begin tmp <= rdata; end
+                                       endcase
+                               end
+                       end
+                       default:
+                               $stop;
                        endcase
                        state <= `STATE_WRITEBACK;
                end
                `STATE_WRITEBACK: begin
                        casex (opcode)
-                               `INSN_LD_reg_imm8:
-                                       case (cycle)
-                                       0: cycle <= 1;
-                                       1: case (opcode[5:3])
-                                               `INSN_imm8_reg_A:       begin registers[`REG_A] <= rdata; cycle <= 0; end
-                                               `INSN_imm8_reg_B:       begin registers[`REG_B] <= rdata; cycle <= 0; end
-                                               `INSN_imm8_reg_C:       begin registers[`REG_C] <= rdata; cycle <= 0; end
-                                               `INSN_imm8_reg_D:       begin registers[`REG_D] <= rdata; cycle <= 0; end
-                                               `INSN_imm8_reg_E:       begin registers[`REG_E] <= rdata; cycle <= 0; end
-                                               `INSN_imm8_reg_H:       begin registers[`REG_H] <= rdata; cycle <= 0; end
-                                               `INSN_imm8_reg_L:       begin registers[`REG_L] <= rdata; cycle <= 0; end
-                                               `INSN_imm8_reg_dHL:     cycle <= 2;
+                       `INSN_LD_reg_imm8:
+                               case (cycle)
+                               0: cycle <= 1;
+                               1: case (opcode[5:3])
+                                       `INSN_reg_A:    begin registers[`REG_A] <= rdata; cycle <= 0; end
+                                       `INSN_reg_B:    begin registers[`REG_B] <= rdata; cycle <= 0; end
+                                       `INSN_reg_C:    begin registers[`REG_C] <= rdata; cycle <= 0; end
+                                       `INSN_reg_D:    begin registers[`REG_D] <= rdata; cycle <= 0; end
+                                       `INSN_reg_E:    begin registers[`REG_E] <= rdata; cycle <= 0; end
+                                       `INSN_reg_H:    begin registers[`REG_H] <= rdata; cycle <= 0; end
+                                       `INSN_reg_L:    begin registers[`REG_L] <= rdata; cycle <= 0; end
+                                       `INSN_reg_dHL:  cycle <= 2;
+                                       endcase
+                               2: cycle <= 0;
+                               endcase
+                       `INSN_HALT: begin
+                               /* Nothing needs happen here. */
+                               /* XXX Interrupts needed for HALT. */
+                       end
+                       `INSN_LD_HL_reg: begin
+                               case (cycle)
+                               0: cycle <= 1;
+                               1: cycle <= 0;
+                               endcase
+                       end
+                       `INSN_LD_reg_HL: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1:      begin
+                                               case (opcode[5:3])
+                                               `INSN_reg_A:    begin registers[`REG_A] <= tmp; end
+                                               `INSN_reg_B:    begin registers[`REG_B] <= tmp; end
+                                               `INSN_reg_C:    begin registers[`REG_C] <= tmp; end
+                                               `INSN_reg_D:    begin registers[`REG_D] <= tmp; end
+                                               `INSN_reg_E:    begin registers[`REG_E] <= tmp; end
+                                               `INSN_reg_H:    begin registers[`REG_H] <= tmp; end
+                                               `INSN_reg_L:    begin registers[`REG_L] <= tmp; end
+                                               endcase
+                                               cycle <= 0;
+                                       end
+                               endcase
+                       end
+                       `INSN_LD_reg_reg: begin
+                               case (opcode[5:3])
+                               `INSN_reg_A:    begin registers[`REG_A] <= tmp; end
+                               `INSN_reg_B:    begin registers[`REG_B] <= tmp; end
+                               `INSN_reg_C:    begin registers[`REG_C] <= tmp; end
+                               `INSN_reg_D:    begin registers[`REG_D] <= tmp; end
+                               `INSN_reg_E:    begin registers[`REG_E] <= tmp; end
+                               `INSN_reg_H:    begin registers[`REG_H] <= tmp; end
+                               `INSN_reg_L:    begin registers[`REG_L] <= tmp; end
+                               endcase
+                       end
+                       `INSN_LD_reg_imm16: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1:      begin
+                                               case (opcode[5:4])
+                                               `INSN_reg16_BC: registers[`REG_C] <= rdata;
+                                               `INSN_reg16_DE: registers[`REG_E] <= rdata;
+                                               `INSN_reg16_HL: registers[`REG_L] <= rdata;
+                                               `INSN_reg16_SP: registers[`REG_SPL] <= rdata;
+                                               endcase
+                                               cycle <= 2;
+                                       end
+                               2: begin
+                                               case (opcode[5:4])
+                                               `INSN_reg16_BC: registers[`REG_B] <= rdata;
+                                               `INSN_reg16_DE: registers[`REG_D] <= rdata;
+                                               `INSN_reg16_HL: registers[`REG_H] <= rdata;
+                                               `INSN_reg16_SP: registers[`REG_SPH] <= rdata;
                                                endcase
-                                       2: cycle <= 0;
+                                               cycle <= 0;
+                                       end
+                               endcase
+                       end
+                       `INSN_LD_SP_HL: begin
+                               case (cycle)
+                               0: begin
+                                               cycle <= 1;
+                                               registers[`REG_SPH] <= tmp;
+                                       end
+                               1: begin
+                                               cycle <= 0;
+                                               registers[`REG_SPL] <= tmp;
+                                       end
+                               endcase
+                       end
+                       `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
+                               case (cycle)
+                               0: begin
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+                                               cycle <= 1;
+                                       end
+                               1:      begin
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+                                               cycle <= 2;
+                                       end
+                               2:      cycle <= 3;
+                               3:      cycle <= 0;
+                               endcase
+                       end
+                       `INSN_POP_reg: begin    /* POP is 12 cycles! */
+                               case (cycle)
+                               0:      begin
+                                               cycle <= 1;
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+                                       end
+                               1:      begin
+                                               case (opcode[5:4])
+                                               `INSN_stack_AF: registers[`REG_F] <= rdata;
+                                               `INSN_stack_BC: registers[`REG_C] <= rdata;
+                                               `INSN_stack_DE: registers[`REG_E] <= rdata;
+                                               `INSN_stack_HL: registers[`REG_L] <= rdata;
+                                               endcase
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+                                               cycle <= 2;
+                                       end
+                               2:      begin
+                                               case (opcode[5:4])
+                                               `INSN_stack_AF: registers[`REG_A] <= rdata;
+                                               `INSN_stack_BC: registers[`REG_B] <= rdata;
+                                               `INSN_stack_DE: registers[`REG_D] <= rdata;
+                                               `INSN_stack_HL: registers[`REG_H] <= rdata;
+                                               endcase
+                                               cycle <= 0;
+                                       end
+                               endcase
+                       end
+                       `INSN_LDH_AC: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1: begin
+                                               cycle <= 0;
+                                               if (opcode[4])
+                                                       registers[`REG_A] <= rdata;
+                                       end
+                               endcase
+                       end
+                       `INSN_LDx_AHL: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1:      begin
+                                               cycle <= 0;
+                                               if (opcode[3])
+                                                       registers[`REG_A] <= rdata;
+                                               {registers[`REG_H],registers[`REG_L]} <=
+                                                       opcode[4] ? // if set, LDD, else LDI
+                                                       ({registers[`REG_H],registers[`REG_L]} - 1) :
+                                                       ({registers[`REG_H],registers[`REG_L]} + 1);
+                                       end
+                               endcase
+                       end
+                       `INSN_ALU8: begin
+                               if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
+                                       /* Sit on our asses. */
+                                       cycle <= 1;
+                               end else begin          /* Actually do the computation! */
+                                       case (opcode[5:3])
+                                       `INSN_alu_ADD: begin
+                                               registers[`REG_A] <=
+                                                       registers[`REG_A] + tmp;
+                                               registers[`REG_F] <=
+                                                       { /* Z */ ((registers[`REG_A] + tmp) == 0) ? 1'b1 : 1'b0,
+                                                         /* N */ 0,
+                                                         /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+                                                         /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+                                                         registers[`REG_F][3:0]
+                                                       };
+                                       end
+                                       default:
+                                               $stop;
                                        endcase
+                               end
+                       end
                        endcase
                        state <= `STATE_FETCH;
                end
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