-VLOGS = 7seg.v GBZ80Core.v insn_call-callcc.v insn_incdec16.v \
- insn_jr-jrcc.v insn_ld_reg_hl.v insn_ld_reg_reg.v insn_nop.v \
- insn_ret-retcc.v Interrupt.v Uart.v allinsns.v insn_alu8.v \
- insn_di-ei.v insn_jp_hl.v insn_ldh_ac.v insn_ld_reg_imm16.v \
- insn_ld_sp_hl.v insn_pop_reg.v insn_rst.v System.v CPUDCM.v \
- insn_alu_a.v insn_halt.v insn_jp-jpcc.v insn_ld_hl_reg.v \
- insn_ld_reg_imm8.v insn_ldx_ahl.v insn_push_reg.v insn_vop_intr.v \
- Timer.v LCDC.v insn_ldm8_a.v insn_ldm16_a.v Framebuffer.v
-
-all: CoreTop_rom.svf CoreTop_diag.svf CoreTop.twr
-
-CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS)
+VLOGS = 7seg.v Framebuffer.v core/GBZ80Core.v Interrupt.v LCDC.v Sound1.v \
+ Sound2.v Soundcore.v System.v Timer.v Uart.v Buttons.v PS2Button.v \
+ Ethernet.v
+
+VLOGS_ALL = $(VLOGS) core/insn_call-callcc.v core/insn_incdec16.v \
+ core/insn_jr-jrcc.v core/insn_ld_reg_hl.v core/insn_ld_reg_reg.v \
+ core/insn_nop.v core/insn_ret-retcc.v core/allinsns.v \
+ core/insn_alu8.v core/insn_di-ei.v core/insn_jp_hl.v \
+ core/insn_ldh_ac.v core/insn_ld_reg_imm16.v core/insn_ld_sp_hl.v \
+ core/insn_pop_reg.v core/insn_rst.v CPUDCM.v core/insn_alu_a.v \
+ core/insn_halt.v core/insn_jp-jpcc.v core/insn_ld_hl_reg.v \
+ core/insn_ld_reg_imm8.v core/insn_ldx_ahl.v core/insn_push_reg.v \
+ core/insn_vop_intr.v core/insn_ldm8_a.v core/insn_ldm16_a.v \
+ core/insn_ldbcde_a.v core/insn_alu_ext.v core/insn_bit.v \
+ core/insn_two_byte.v core/insn_incdec_reg8.v core/insn_add_hl.v \
+ core/insn_add_sp_imm8.v core/insn_ldhl_sp_imm8.v core/insn_ld_nn_sp.v \
+ core/insn_setres.v
+
+all: CoreTop.svf
+
+sim: CoreTop_isim.exe
+
+CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS_ALL) fpgaboot.hex gbboot.hex
git.joshuawise.com / fpgaboy.git / blobdiff