Add cut 1 of a cellram module

[fpgaboy.git] / LCDC.v

diff --git a/LCDC.v b/LCDC.v
index 444fb85b02792a7055e84f49fe356b87e2563654..a198c45d03ad806e4987cf3c3b7455ee9e704745 100644 (file)
--- a/LCDC.v
+++ b/LCDC.v
@@ -19,26 +19,18 @@ module LCDC(
        output wire lcdcirq,
        output wire vblankirq,
        output wire lcdclk, lcdvs, lcdhs,
        output wire lcdcirq,
        output wire vblankirq,
        output wire lcdclk, lcdvs, lcdhs,

-       output wire [2:0] lcdr, lcdg, output wire [1:0] lcdb);
+       output reg [2:0] lcdr, lcdg, output reg [1:0] lcdb);
+       
+       /***** Needed prototypes *****/
+       wire [1:0] pixdata;

        
        /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
        reg clk4 = 0;
        always @(posedge clk)
        
        /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
        reg clk4 = 0;
        always @(posedge clk)

-               clk4 = ~clk4;
-       assign lcdclk = clk4;
-       
-       /***** Video RAM *****/
-       /* Base is 0x8000
-        *
-        * Tile data from 8000-8FFF or 8800-97FF
-        * Background tile maps 9800-9BFF or 9C00-9FFF
-        */
-       reg [7:0] tiledata [6143:0];
-       reg [7:0] bgmap1 [1023:0];
-       reg [7:0] bgmap2 [1023:0];
+               clk4 <= ~clk4;

        
        /***** LCD control registers *****/
        
        /***** LCD control registers *****/

-       reg [7:0] rLCDC = 8'h91;
+       reg [7:0] rLCDC = 8'h00;

        reg [7:0] rSTAT = 8'h00;
        reg [7:0] rSCY = 8'b00;
        reg [7:0] rSCX = 8'b00;
        reg [7:0] rSTAT = 8'h00;
        reg [7:0] rSCY = 8'b00;
        reg [7:0] rSCX = 8'b00;


@@ -57,11 +49,11 @@ module LCDC(
         *
         * Modes: 0 -> in hblank and OAM/VRAM available - present 207 clks
         *        1 -> in vblank and OAM/VRAM available
         *
         * Modes: 0 -> in hblank and OAM/VRAM available - present 207 clks
         *        1 -> in vblank and OAM/VRAM available

-        *        2 -> OAM in use - present 83 clks
-        *        3 -> OAM/VRAM in use - present 166 clks
-        * So, X = 0~165 is HActive,
-        * X = 166-372 is HBlank,
-        * X = 373-455 is HWhirrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr.
+        *        2 -> OAM in use - present 86 clks
+        *        3 -> OAM/VRAM in use - present 163 clks
+        * So, X = 0~162 is HActive,
+        * X = 163-369 is HBlank,
+        * X = 370-455 is HWhirrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr.

         * [02:15:10] <Judge_> LY is updated near the 0 -> 2 transition
         * [02:15:38] <Judge_> it seems to be updated internally first before it is visible in the LY register itself
         * [02:15:40] <Judge_> some kind of delay
         * [02:15:10] <Judge_> LY is updated near the 0 -> 2 transition
         * [02:15:38] <Judge_> it seems to be updated internally first before it is visible in the LY register itself
         * [02:15:40] <Judge_> some kind of delay


@@ -69,17 +61,28 @@ module LCDC(
         */
        reg [8:0] posx = 9'h000;
        reg [7:0] posy = 8'h00;
         */
        reg [8:0] posx = 9'h000;
        reg [7:0] posy = 8'h00;

+       
+       wire vraminuse = (posx < 163) && (posy < 144) && rLCDC[7];
+       wire oaminuse = (posx > 369) && (posy < 144) && rLCDC[7];
+       
+       wire display = (posx > 2) && (posx < 163) && (posy < 144);
+       

        wire [1:0] mode = (posy < 144) ?
        wire [1:0] mode = (posy < 144) ?

-                               ((posx < 166) ? 2'b11 :
-                                (posx < 373) ? 2'b00 :
-                                2'b10)
+                               (vraminuse ? 2'b11 :
+                                oaminuse ? 2'b10 :
+                                2'b00)

                                : 2'b01;
        
                                : 2'b01;
        

-       assign lcdvs = (posy == 153) && (posx == 455);
-       assign lcdhs = (posx == 455);
-       assign lcdr = (posx < 160) && (posy < 144) ? {posy == rLYC ? 3'b111 : 3'b000} : 3'b000;
-       assign lcdg = (posx < 160) && (posy < 144) ? {posy < rSCY ? 3'b111 : 3'b000} : 3'b000;
-       assign lcdb = (posx < 160) && (posy < 144) ? {2'b11} : 2'b00;
+       wire [7:0] vxpos = rSCX + posx - 3;
+       wire [7:0] vypos = rSCY + posy;
+       
+       assign lcdvs = (posy == 153) && (posx == 2) && rLCDC[7];
+       assign lcdhs = (posx == 2) && rLCDC[7];
+       assign lcdclk = clk4;
+       
+       wire [2:0] lcdr_ = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000;
+       wire [2:0] lcdg_ = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000;
+       wire [1:0] lcdb_ = display ? {(vypos < 8 || vxpos < 8) ? 2'b11 : 2'b00} : 2'b00;

        
        reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;
        assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);
        
        reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;
        assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);


@@ -117,25 +120,77 @@ module LCDC(
                        lycirq <= 0;
                end
                
                        lycirq <= 0;
                end
                

+               lcdr <= lcdr_;
+               lcdg <= lcdg_;
+               lcdb <= lcdb_;
+       end
+       
+       /***** Video RAM *****/
+       /* Base is 0x8000
+        *
+        * Tile data from 8000-8FFF or 8800-97FF
+        * Background tile maps 9800-9BFF or 9C00-9FFF
+        */
+       reg [7:0] tiledatahigh [3071:0];
+       reg [7:0] tiledatalow [3071:0];
+       reg [7:0] bgmap1 [1023:0];
+       reg [7:0] bgmap2 [1023:0];
+       
+       // Upper five bits are Y coord, lower five bits are X coord
+       // The new tile number is loaded when vxpos[2:0] is 3'b110
+       // The new tile data is loaded when vxpos[2:0] is 3'b111
+       // The new tile data is latched and ready when vxpos[2:0] is 3'b000!
+       wire [7:0] vxpos_ = vxpos + 1;
+       wire [9:0] bgmapaddr = {vypos[7:3], vxpos_[7:3]};
+       reg [7:0] tileno;
+       wire [10:0] tileaddr = {tileno, vypos[2:0]};
+       reg [7:0] tilehigh, tilelow;
+       wire [1:0] prepal = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]};
+       assign pixdata = {rBGP[{prepal,1'b1}],rBGP[{prepal,1'b0}]};
+       
+       wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF);
+       wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF);
+
+       wire [9:0] bgmapaddr_in = vraminuse ? bgmapaddr : addr[9:0];
+       wire [11:0] tileaddr_in = vraminuse ? tileaddr : addr[12:1];
+       
+       always @(posedge clk)
+       begin
+               if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_bgmap1) begin
+                       tileno <= bgmap1[bgmapaddr_in];
+                       if (wr && decode_bgmap1 && ~vraminuse)
+                               bgmap1[bgmapaddr_in] <= data;
+               end
+               if ((vraminuse && ((posx == 3) || (vxpos[2:0] == 3'b000))) || decode_tiledata) begin
+                       tilehigh <= tiledatahigh[tileaddr_in];
+                       tilelow <= tiledatalow[tileaddr_in];
+                       if (wr && addr[0] && decode_tiledata && ~vraminuse)
+                               tiledatahigh[tileaddr_in] <= data;
+                       if (wr && ~addr[0] && decode_tiledata && ~vraminuse)
+                               tiledatalow[tileaddr_in] <= data;
+               end

        end
   
        /***** Bus interface *****/
        assign data = rd ?
        end
   
        /***** Bus interface *****/
        assign data = rd ?

-                       (addr == `ADDR_LCDC) ? rLCDC :
-                       (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
-                       (addr == `ADDR_SCY) ? rSCY :
-                       (addr == `ADDR_SCX) ? rSCX :
-                       (addr == `ADDR_LY) ? posy :
-                       (addr == `ADDR_LYC) ? rLYC :
-                       (addr == `ADDR_BGP) ? rBGP :
-                       (addr == `ADDR_OBP0) ? rOBP0 :
-                       (addr == `ADDR_OBP1) ? rOBP1 :
-                       (addr == `ADDR_WY) ? rWY :
-                       (addr == `ADDR_WX) ? rWX :
-                       8'bzzzzzzzz :
+                       ((addr == `ADDR_LCDC) ? rLCDC :
+                        (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
+                        (addr == `ADDR_SCY) ? rSCY :
+                        (addr == `ADDR_SCX) ? rSCX :
+                        (addr == `ADDR_LY) ? posy :
+                        (addr == `ADDR_LYC) ? rLYC :
+                        (addr == `ADDR_BGP) ? rBGP :
+                        (addr == `ADDR_OBP0) ? rOBP0 :
+                        (addr == `ADDR_OBP1) ? rOBP1 :
+                        (addr == `ADDR_WY) ? rWY :
+                        (addr == `ADDR_WX) ? rWX :
+                        (decode_tiledata && addr[0]) ? tilehigh :
+                        (decode_tiledata && ~addr[0]) ? tilelow :
+                        (decode_bgmap1) ? tileno :
+                        8'bzzzzzzzz) :

                8'bzzzzzzzz;
   
                8'bzzzzzzzz;
   

-       always @(negedge clk)
+       always @(posedge clk)

        begin
                if (wr)
                        case (addr)
        begin
                if (wr)
                        case (addr)