Merge branch 'master' of lu@anyus.res.cmu.edu:/storage/fpga/FPGABoy
[fpgaboy.git] / Uart.v
diff --git a/Uart.v b/Uart.v
index 332620b..ab16d79 100644 (file)
--- a/Uart.v
+++ b/Uart.v
@@ -27,7 +27,7 @@ module UART(
        reg rx_hasdata = 0;
        reg [15:0] rx_clkdiv = 0;
        reg [3:0] rx_state = 4'b0000;
-       reg [7:0] rx_data;
+       reg [7:0] rx_data, rx_data_tmp;
        
        assign data = (stat_latch) ? {6'b0, rx_hasdata, tx_busy} :
                        (data_latch) ? rx_data :
@@ -69,19 +69,23 @@ module UART(
                                rx_state <= 0;
                        case (rx_state)
                        4'b0001:        begin end /* Twiddle thumbs -- this is the end of the half bit. */
-                       4'b0010:        rx_data[0] <= serialrx;
-                       4'b0011:        rx_data[1] <= serialrx;
-                       4'b0100:        rx_data[2] <= serialrx;
-                       4'b0101:        rx_data[3] <= serialrx;
-                       4'b0110:        rx_data[4] <= serialrx;
-                       4'b0111:        rx_data[5] <= serialrx;
-                       4'b1000:        rx_data[6] <= serialrx;
-                       4'b1001:        rx_data[7] <= serialrx;
-                       4'b1010:        begin end /* Expect a 1 */
+                       4'b0010:        rx_data_tmp[0] <= serialrx;
+                       4'b0011:        rx_data_tmp[1] <= serialrx;
+                       4'b0100:        rx_data_tmp[2] <= serialrx;
+                       4'b0101:        rx_data_tmp[3] <= serialrx;
+                       4'b0110:        rx_data_tmp[4] <= serialrx;
+                       4'b0111:        rx_data_tmp[5] <= serialrx;
+                       4'b1000:        rx_data_tmp[6] <= serialrx;
+                       4'b1001:        rx_data_tmp[7] <= serialrx;
+                       4'b1010:        if (serialrx == 1) begin
+                                               rx_data <= rx_data_tmp; /* Expect a 1 */
+                                               rx_hasdata <= 1;
+                                       end
                        endcase
                end
                
-               rx_hasdata <= (rx_hasdata && ~(rd && data_decode)) || ((rx_state == 4'b1010) && (tx_clkdiv == 0));
+               if (rd && data_decode)
+                       rx_hasdata <= 0;
 
                if(tx_newdata || (tx_clkdiv == `CLK_DIV))
                        tx_clkdiv <= 0;
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