Merge branch 'master' of lu@anyus.res.cmu.edu:/storage/fpga/FPGABoy

[fpgaboy.git] / LCDC.v

diff --git a/LCDC.v b/LCDC.v
index a198c45d03ad806e4987cf3c3b7455ee9e704745..cb204d5df1e5c6b58b0761cd4474c099f6abf946 100644 (file)
--- a/LCDC.v
+++ b/LCDC.v
@@ -21,6 +21,10 @@ module LCDC(
        output wire lcdclk, lcdvs, lcdhs,
        output reg [2:0] lcdr, lcdg, output reg [1:0] lcdb);
        
+       /***** Bus latches *****/
+       reg rdlatch = 0;
+       reg [15:0] addrlatch = 0;
+       
        /***** Needed prototypes *****/
        wire [1:0] pixdata;
        
@@ -146,7 +150,7 @@ module LCDC(
        wire [10:0] tileaddr = {tileno, vypos[2:0]};
        reg [7:0] tilehigh, tilelow;
        wire [1:0] prepal = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]};
-       assign pixdata = {rBGP[{prepal,1'b1}],rBGP[{prepal,1'b0}]};
+       assign pixdata = 2'b11-{rBGP[{prepal,1'b1}],rBGP[{prepal,1'b0}]};
        
        wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF);
        wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF);
@@ -172,26 +176,28 @@ module LCDC(
        end
   
        /***** Bus interface *****/
-       assign data = rd ?
-                       ((addr == `ADDR_LCDC) ? rLCDC :
-                        (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
-                        (addr == `ADDR_SCY) ? rSCY :
-                        (addr == `ADDR_SCX) ? rSCX :
-                        (addr == `ADDR_LY) ? posy :
-                        (addr == `ADDR_LYC) ? rLYC :
-                        (addr == `ADDR_BGP) ? rBGP :
-                        (addr == `ADDR_OBP0) ? rOBP0 :
-                        (addr == `ADDR_OBP1) ? rOBP1 :
-                        (addr == `ADDR_WY) ? rWY :
-                        (addr == `ADDR_WX) ? rWX :
-                        (decode_tiledata && addr[0]) ? tilehigh :
-                        (decode_tiledata && ~addr[0]) ? tilelow :
+       assign data = rdlatch ?
+                       ((addrlatch == `ADDR_LCDC) ? rLCDC :
+                        (addrlatch == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
+                        (addrlatch == `ADDR_SCY) ? rSCY :
+                        (addrlatch == `ADDR_SCX) ? rSCX :
+                        (addrlatch == `ADDR_LY) ? posy :
+                        (addrlatch == `ADDR_LYC) ? rLYC :
+                        (addrlatch == `ADDR_BGP) ? rBGP :
+                        (addrlatch == `ADDR_OBP0) ? rOBP0 :
+                        (addrlatch == `ADDR_OBP1) ? rOBP1 :
+                        (addrlatch == `ADDR_WY) ? rWY :
+                        (addrlatch == `ADDR_WX) ? rWX :
+                        (decode_tiledata && addrlatch[0]) ? tilehigh :
+                        (decode_tiledata && ~addrlatch[0]) ? tilelow :
                         (decode_bgmap1) ? tileno :
                         8'bzzzzzzzz) :
                8'bzzzzzzzz;
   
        always @(posedge clk)
        begin
+               rdlatch <= rd;
+               addrlatch <= addr;
                if (wr)
                        case (addr)
                        `ADDR_LCDC:     rLCDC <= data;