Cut 1 at ADD HL,...

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 3c2f7702aaa1c9e507232c435029c0a4456f48cf..053df4a1a4619c6a8eaf7a220ff21d6bd9418f3a 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -79,6 +79,7 @@
 `define INSN_BIT               9'b101xxxxxx
 `define INSN_RES               9'b110xxxxxx
 `define INSN_SET               9'b111xxxxxx
+`define INSN_ADD_HL            9'b000xx1001
 
 `define INSN_cc_NZ             2'b00
 `define INSN_cc_Z              2'b01
@@ -152,7 +153,7 @@ module GBZ80Core(
        inout [15:0] bus1address,       /* BUS_* is latched on STATE_FETCH. */
        inout [7:0] bus1data,
        inout bus1wr, bus1rd,
-       input irq, input [7:0] jaddr,
+       input irq, output reg irqack, input [7:0] jaddr,
        output reg [1:0] state);
 
 //     reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */
@@ -282,6 +283,7 @@ module GBZ80Core(
                cycle <= 0;
                twobyte <= 0;
                bootstrap_enb <= 1;
+               irqack <= 0;
        end
 
        always @(negedge clk)   /* Set things up at the negedge to prepare for the posedge. */
@@ -341,8 +343,10 @@ module GBZ80Core(
                        state <= `STATE_EXECUTE;
                end
                `STATE_EXECUTE: begin
+               `ifdef isim
                        if (opcode[7:0] === 8'bxxxxxxxx)
                                $stop;
+               `endif
                        casex (opcode)
                        `define EXECUTE
                        `include "allinsns.v"