Make it easy to see what's going wrong.

[fpgaboy.git] / Uart.v

diff --git a/Uart.v b/Uart.v
index f87005dfc2aaa9b0b5af9fc322acec14a78c5c2f..af173ca63281605658f6f20c97ec4b88fce3a252 100644 (file)
--- a/Uart.v
+++ b/Uart.v
@@ -1,5 +1,5 @@
 `define IN_CLK 8388608
-`define OUT_CLK 9600
+`define OUT_CLK 57600
 `define CLK_DIV `IN_CLK / `OUT_CLK
 `define MMAP_ADDR 16'hFF50
 
@@ -19,7 +19,6 @@ module UART(
        reg [7:0] data_stor = 0;
        reg [15:0] clkdiv = 0;
        reg have_data = 0;
-       reg data_end = 0;
        reg [3:0] diqing = 4'b0000;
        
        wire new = (wr) && (!have_data) && decode;