Add DI/EI delay test. Add LD M, A.

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 00ee4ecee5d67c006b0adc276aac752eede763ed..5b0fb3cc45f05c81f58e96f7263b386e4eaf1619 100644 (file)
--- a/System.v
+++ b/System.v
@@ -72,10 +72,6 @@ module CoreTop(
        wire clk;       
        CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
        
-       wire cclk;
-//     IBUFG ibuf (.O(cclk), .I(switches[0] & clk));
-       assign cclk = clk;
-
        wire [15:0] addr;       
        wire [7:0] data;
        wire wr, rd;
@@ -120,7 +116,7 @@ module CoreTop(
                .wr(wr),
                .rd(rd),
                .ledout(leds),
-               .switches({switches[7:1],1'b0})
+               .switches(switches)
                );
 
        UART nouart (   /* no u */