Set up the bus a little before the clock.

[fpgaboy.git] / Timer.v

diff --git a/Timer.v b/Timer.v
index 0481614f5c97586672ba16ed34265b0dcc04b4da..53f392deae20118ea451112fa123cf2a83391075 100644 (file)
--- a/Timer.v
+++ b/Timer.v
@@ -9,11 +9,11 @@ module Timer(
        input rd,
        input [15:0] addr,
        inout [7:0] data,
-       output reg irq);
+       output reg irq = 0);
 
        reg [7:0] tima = 0, tma = 0, tac = 0, div = 0;
        reg ovf = 0;
-       reg [9:0] clkdv;
+       reg [9:0] clkdv = 0;
 
        wire is_tima = addr == `ADDR_TIMA;
        wire is_tma  = addr == `ADDR_TMA;