Set up the bus a little before the clock.

[fpgaboy.git] / Interrupt.v

diff --git a/Interrupt.v b/Interrupt.v
index 4e3d17d6312e59ea8966fa659e0c1e88a096ec69..1450b2cfd0b6ecf8c61e76f7ab8894cc96a3efe4 100644 (file)
--- a/Interrupt.v
+++ b/Interrupt.v
@@ -17,7 +17,7 @@ module Interrupt(
 
        wire [7:0] iflag = {3'b0,buttons,serial,tovf,lcdc,vblank};
        reg [7:0] imask = 16'hFFFF;
-       reg [7:0] ihold = 0;
+       reg [7:0] ihold = 8'b0;
        wire [7:0] imasked = ihold & imask;
 
        assign data = rd ?
@@ -34,12 +34,12 @@ module Interrupt(
                       imasked[3] ? 8'h58 :
                       imasked[4] ? 8'h60 : 8'h00;
 
-       always @ (negedge clk)
+       always @(negedge clk)
        begin
-               if (wr) begin
+               if (wr && (addr == `ADDR_IF || addr == `ADDR_IE)) begin
                        case(addr)
                        `ADDR_IF : ihold <= iflag | data;
-                       `ADDR_IE : imask <= data;
+                       `ADDR_IE : begin imask <= data; ihold <= ihold | iflag; end
                        endcase
                        
                end