Timer works.

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index a5fee66e243e92a9079e66331d929075fe2e120d..8b8d61344f712e4c39cfae009bf71969f67039a9 100644 (file)
--- a/System.v
+++ b/System.v
@@ -151,7 +151,7 @@ module CoreTop(
 endmodule
 
 module TestBench();
-       reg clk = 0;
+       reg clk = 1;
        wire [15:0] addr;
        wire [7:0] data;
        wire wr, rd;