Timer works.

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 96e4dcd38a164996df038dca0232ab82a837e90e..095d9e85e555d592bcdcca33ae6f23bee3ca663d 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -87,9 +87,9 @@
 
 module GBZ80Core(
        input clk,
-       output reg [15:0] busaddress,   /* BUS_* is latched on STATE_FETCH. */
+       output reg [15:0] busaddress = 0,       /* BUS_* is latched on STATE_FETCH. */
        inout [7:0] busdata,
-       output reg buswr, output reg busrd);
+       output reg buswr = 0, output reg busrd = 0);
        
        reg [1:0] state = 0;                                    /* State within this bus cycle (see STATE_*). */
        reg [2:0] cycle = 0;                                    /* Cycle for instructions. */