ld c, $51 ; Note that we are alive.
ld a, $FF
ld [c],a
-
+
ld sp, $DFFF
ld hl, signon
call puts
+
+ ld c, $07
+ ld a, $04 ;start timer, 4.096KHz
+ ld [c], a
+ ei
call memtest
call insntest
call waitsw
+ di
jr main
+ section "fuq",HOME[$100]
+irqhand:
+ PUSH AF
+ PUSH BC
+ PUSH DE
+ PUSH HL
+ xor a
+ ld c, $0F ; ack the irq
+ ld [c], a
+ ld a, $41 ; print A
+ call putc
+ POP HL
+ POP DE
+ POP BC
+ POP AF
+ RETI
+
signon:
db $0D,$0A,$1B,"[1mFPGABoy Diagnostic ROM",$1B,"[0m",$0D,$0A,0
waitsw:
ld hl,waitswstr
call puts
-
- ld c, $07
- ld a, $07 ;start timer, 4.096KHz
- ld [c], a
-
+
ld c, $51
- ld a, $00
+ xor a
ld [c],a
-.loop1:
- push bc
- call testa
- pop bc
- ld c, $51
ld b, $0
+.loop1:
ld a,[c]
cp b
jr z,.loop1
waitswstr:
db "Diagnostic ROM complete; flip switches to nonzero and then to zero to reset. Expect A.",$0D,$0A,0
-testa:
- ld c, $0F
- ld a, [c]
- ld b, $00
- cp b
- ret z
- xor a
- ld [c], a
- ld hl, $D000
- ld c, [hl]
- inc bc
- ld [hl], c
- ld a, c
- ld c, $50
- ld [c], a
- ret
-
; Core instruction basic acceptance tests.
insntest:
ld hl, .insnteststr
putc:
ld b, 0
ld c, $50
+ push af
.waitport:
ld a,[c]
cp b
jr nz,.waitport
+ pop af
ld [c],a
ret
ld a, [hli]
ld b, $00
cp b
- ret z
+ jr z, .done
call putc
jr puts
+.done:
+ ret