and verified

[fpgaboy.git] / Sound1.v

diff --git a/Sound1.v b/Sound1.v
index 41abaa539e844f84f72d0cf890a45297b8450a4b..ca97b174ce40c410423a405ea3f777565045a55e 100644 (file)
--- a/Sound1.v
+++ b/Sound1.v
@@ -23,18 +23,23 @@ module Sound1(
        reg [3:0] delta = 4'b1111;
        reg toggle = 0;
        reg [3:0] snd_out = 0;
+       
+       reg rdlatch;
+       reg [15:0] addrlatch;
 
        assign snd_data = en ? snd_out : 0;
 
-       assign data = rd ?
-                        addr == `ADDR_NR10 ? nr10 :
-                        addr == `ADDR_NR11 ? nr11 :
-                        addr == `ADDR_NR12 ? nr12 :
-                        addr == `ADDR_NR13 ? nr13 :
-                        addr == `ADDR_NR14 ? nr14 : 8'bzzzzzzzz
+       assign data = rdlatch ?
+                        addrlatch == `ADDR_NR10 ? nr10 :
+                        addrlatch == `ADDR_NR11 ? nr11 :
+                        addrlatch == `ADDR_NR12 ? nr12 :
+                        addrlatch == `ADDR_NR13 ? nr13 :
+                        addrlatch == `ADDR_NR14 ? nr14 : 8'bzzzzzzzz
                      : 8'bzzzzzzzz;
 
-       always @ (negedge core_clk) begin
+       always @ (posedge core_clk) begin
+               rdlatch <= rd;
+               addrlatch <= addr;
                if(en && wr) begin
                        case(addr)
                        `ADDR_NR10: nr10 <= data;