Cut one at a framebuffer

[fpgaboy.git] / LCDC.v

diff --git a/LCDC.v b/LCDC.v
index 622094aadd0e281f1c4ccaadd3584ee307733e5c..05a46d5cfab751054e53f5f2dc3d5f4b31bb37aa 100644 (file)
--- a/LCDC.v
+++ b/LCDC.v
@@ -18,13 +18,14 @@ module LCDC(
        input wr, rd,
        output wire lcdcirq,
        output wire vblankirq,
-       output wire vgavs, vgahs,
-       output wire [2:0] vgar, vgag, output wire [1:0] vgab);
+       output wire lcdclk, lcdvs, lcdhs,
+       output wire [2:0] lcdr, lcdg, output wire [1:0] lcdb);
        
        /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
        reg clk4 = 0;
        always @(posedge clk)
                clk4 = ~clk4;
+       assign lcdclk = clk4;
        
        /***** LCD control registers *****/
        reg [7:0] rLCDC = 8'h91;
@@ -51,6 +52,10 @@ module LCDC(
         * So, X = 0~165 is HActive,
         * X = 166-372 is HBlank,
         * X = 373-455 is HWhirrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr.
+        * [02:15:10] <Judge_> LY is updated near the 0 -> 2 transition
+        * [02:15:38] <Judge_> it seems to be updated internally first before it is visible in the LY register itself
+        * [02:15:40] <Judge_> some kind of delay
+        * [02:16:19] <Judge_> iirc it is updated about 4 cycles prior to mode 2
         */
        reg [8:0] posx = 9'h000;
        reg [7:0] posy = 8'h00;
@@ -60,11 +65,11 @@ module LCDC(
                                 2'b10)
                                : 2'b01;
        
-       assign vgavs = (posy > 147) && (posy < 151);
-       assign vgahs = (posx < 250) && (posx < 350);
-       assign vgar = (posx < 160) && (posy < 144) ? {posy == rLYC ? 3'b111 : 3'b000} : 3'b000;
-       assign vgag = (posx < 160) && (posy < 144) ? {posy < rSCY ? 3'b111 : 3'b000} : 3'b000;
-       assign vgab = (posx < 160) && (posy < 144) ? {2'b11} : 2'b00;
+       assign lcdvs = (posy == 153) && (posx == 455);
+       assign lcdhs = (posx == 455);
+       assign lcdr = (posx < 160) && (posy < 144) ? {posy == rLYC ? 3'b111 : 3'b000} : 3'b000;
+       assign lcdg = (posx < 160) && (posy < 144) ? {posy < rSCY ? 3'b111 : 3'b000} : 3'b000;
+       assign lcdb = (posx < 160) && (posy < 144) ? {2'b11} : 2'b00;
        
        reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;
        assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);