YET UNIMPLEMENTED: imm3 = 3-bit immediate value in 8 bits imm8 = 8-bit immediate value imm16 = 16-bit immediate value 16m8 = 8-bit value at the 16-bit address 8m8 = 8-bit value at the 8-bit address (the 16-bit equivalent is 0xFF00 + addr) bits insn notes 0000 1000 LD 16m16,SP loads SP 0000 1001 ADD HL, BC 0001 0000 STOP 0001 1001 ADD HL, DE 0010 1001 ADD HL, HL 0011 1001 ADD HL, SP 0111 0110 HALT Danger! Helvetica! 1100 1011 - - - see two-byte opcodes below 1110 1000 ADD SP, imm8 1111 1000 LDHL SP, imm8 load SP+n (signed n) into HL ***************************** fucking two-byte opcodes bits insn notes 1100 1011 0000 0000 RLC B 1100 1011 0000 0001 RLC C 1100 1011 0000 0010 RLC D 1100 1011 0000 0011 RLC E 1100 1011 0000 0100 RLC H 1100 1011 0000 0101 RLC L 1100 1011 0000 0110 RLC (HL) 1100 1011 0000 0111 RLC A 1100 1011 0000 1000 RRC B 1100 1011 0000 1001 RRC C 1100 1011 0000 1010 RRC D 1100 1011 0000 1011 RRC E 1100 1011 0000 1100 RRC H 1100 1011 0000 1101 RRC L 1100 1011 0000 1110 RRC (HL) 1100 1011 0000 1111 RRC A 1100 1011 0001 0000 RL B 1100 1011 0001 0001 RL C 1100 1011 0001 0010 RL D 1100 1011 0001 0011 RL E 1100 1011 0001 0100 RL H 1100 1011 0001 0101 RL L 1100 1011 0001 0110 RL (HL) 1100 1011 0001 0111 RL A 1100 1011 0001 1000 RR B 1100 1011 0001 1001 RR C 1100 1011 0001 1010 RR D 1100 1011 0001 1011 RR E 1100 1011 0001 1100 RR H 1100 1011 0001 1101 RR L 1100 1011 0001 1110 RR (HL) 1100 1011 0001 1111 RR A 1100 1011 0010 0000 SLA B 1100 1011 0010 0001 SLA C 1100 1011 0010 0010 SLA D 1100 1011 0010 0011 SLA E 1100 1011 0010 0100 SLA H 1100 1011 0010 0101 SLA L 1100 1011 0010 0110 SLA (HL) 1100 1011 0010 0111 SLA A 1100 1011 0010 1000 SRA B 1100 1011 0010 1001 SRA C 1100 1011 0010 1010 SRA D 1100 1011 0010 1011 SRA E 1100 1011 0010 1100 SRA H 1100 1011 0010 1101 SRA L 1100 1011 0010 1110 SRA (HL) 1100 1011 0010 1111 SRA A 1100 1011 0011 1000 SRL B 1100 1011 0011 1001 SRL C 1100 1011 0011 1010 SRL D 1100 1011 0011 1011 SRL E 1100 1011 0011 1100 SRL H 1100 1011 0011 1101 SRL L 1100 1011 0011 1110 SRL (HL) 1100 1011 0011 1111 SRL A 1100 1011 0011 0000 SWAP B swaps upper and lower nibbles of a byte 1100 1011 0011 0001 SWAP C 1100 1011 0011 0010 SWAP D 1100 1011 0011 0011 SWAP E 1100 1011 0011 0100 SWAP H 1100 1011 0011 0101 SWAP L 1100 1011 0011 0110 SWAP (HL) 1100 1011 0011 0111 SWAP A 1100 1011 1000 0000 RES imm3, B reset bit specified by imm3 1100 1011 1000 0001 RES imm3, C 1100 1011 1000 0010 RES imm3, D 1100 1011 1000 0011 RES imm3, E 1100 1011 1000 0100 RES imm3, H 1100 1011 1000 0101 RES imm3, L 1100 1011 1000 0110 RES imm3, (HL) 1100 1011 1000 0111 RES imm3, A 1100 1011 1100 0000 SET imm3, B set bit specified by imm3 1100 1011 1100 0001 SET imm3, C 1100 1011 1100 0010 SET imm3, D 1100 1011 1100 0011 SET imm3, E 1100 1011 1100 0100 SET imm3, H 1100 1011 1100 0101 SET imm3, L 1100 1011 1100 0110 SET imm3, (HL) 1100 1011 1100 0111 SET imm3, A