`define INSN_ALU_EXT 9'b100xxxxxx `ifdef LOCALWIRES wire [7:0] rlc,rrc,rl,rr,sla,sra,swap,srl; wire [3:0] rlcf,rrcf,rlf,rrf,slaf,sraf,swapf,srlf; wire [7:0] alu_res; wire [3:0] f_res; assign rlc = {tmp[6:0],tmp[7]}; assign rlcf = {(tmp == 0 ? 1'b1 : 1'b0) ,2'b0, tmp[7]}; assign rrc = {tmp[0],tmp[7:1]}; assign rrcf = {(tmp == 0 ? 1'b1 : 1'b0), 2'b0, tmp[0]}; assign rl = {tmp[6:0],`_F[4]}; assign rlf = {({tmp[6:0],`_F[4]} == 0 ? 1'b1 : 1'b0), 2'b0, tmp[7]}; assign rr = {`_F[4],tmp[7:1]}; assign rrf = {({`_F[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0), 2'b0, tmp[0]}; assign sla = {tmp[6:0],1'b0}; assign slaf = {(tmp[6:0] == 0 ? 1'b1 : 1'b0), 2'b0, tmp[7]}; assign sra = {tmp[7],tmp[7:1]}; // assign sraf = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]}; now in assign srlf = assign swap = {tmp[3:0],tmp[7:4]}; assign swapf = {(tmp == 1'b0 ? 1'b1 : 1'b0), 3'b0}; assign srl = {1'b0,tmp[7:1]}; assign srlf = {(tmp[7:1] == 0 ? 1'b1 : 1'b0), 2'b0, tmp[0]}; assign sraf = srlf; /* Y U Q */ assign {alu_res,f_res} = opcode[5] ? ( opcode[4] ? ( opcode[3] ? {srl,srlf} : {swap,swapf} ) : ( opcode[3] ? {sra,sraf} : {sla,slaf} ) ) : ( opcode[4] ? ( opcode[3] ? {rr,rrf} : {rl,rlf} ) : ( opcode[3] ? {rrc,rrcf} : {rlc,rlcf} ) ); `endif `ifdef EXECUTE `INSN_ALU_EXT: begin if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) `EXEC_READ(`_HL) else begin `EXEC_INC_PC case (opcode[2:0]) `INSN_reg_A: tmp <= `_A; `INSN_reg_B: tmp <= `_B; `INSN_reg_C: tmp <= `_C; `INSN_reg_D: tmp <= `_D; `INSN_reg_E: tmp <= `_E; `INSN_reg_H: tmp <= `_H; `INSN_reg_L: tmp <= `_L; `INSN_reg_dHL: tmp <= rdata; endcase end end `endif `ifdef WRITEBACK `INSN_ALU_EXT: begin if (opcode[2:0] == `INSN_reg_dHL) begin if(cycle == 0) begin end else if(cycle == 1) begin `EXEC_WRITE(`_HL, alu_res) `_F <= {f_res,`_F[3:0]}; end else begin `EXEC_NEWCYCLE end end else begin case(opcode[2:0]) `INSN_reg_B: `_B <= alu_res; `INSN_reg_C: `_C <= alu_res; `INSN_reg_D: `_D <= alu_res; `INSN_reg_E: `_E <= alu_res; `INSN_reg_H: `_H <= alu_res; `INSN_reg_L: `_L <= alu_res; `INSN_reg_A: `_A <= alu_res; `INSN_reg_dHL: begin end /* eat dicks */ endcase `_F <= {f_res,`_F[3:0]}; `EXEC_NEWCYCLE end end `endif