//////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. //////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version : 10.1 // \ \ Application : xaw2verilog // / / Filename : CPUDCM.v // /___/ /\ Timestamp : 03/31/2008 23:51:44 // \ \ / \ // \___\/\___\ // //Command: xaw2verilog -intstyle /home/joshua/projects/fpga/FPGABoy/CPUDCM.xaw -st CPUDCM.v //Design Name: CPUDCM //Device: xc3s500e-5fg320 // // Module CPUDCM // Generated by Xilinx Architecture Wizard // Written for synthesis tool: XST // Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI // Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 4.90 ns `timescale 1ns / 1ps module CPUDCM(CLKIN_IN, CLKFX_OUT, CLKIN_IBUFG_OUT, LOCKED_OUT); input CLKIN_IN; output CLKFX_OUT; output CLKIN_IBUFG_OUT; output LOCKED_OUT; wire CLKFX_BUF; wire CLKIN_IBUFG; wire GND_BIT; assign GND_BIT = 0; assign CLKIN_IBUFG_OUT = CLKIN_IBUFG; BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), .O(CLKFX_OUT)); DCM_SP DCM_SP_INST (.CLKFB(GND_BIT), .CLKIN(CLKIN_IN), .DSSEN(GND_BIT), .PSCLK(GND_BIT), .PSEN(GND_BIT), .PSINCDEC(GND_BIT), .RST(GND_BIT), .CLKDV(), .CLKFX(CLKFX_BUF), .CLKFX180(), .CLK0(), .CLK2X(), .CLK2X180(), .CLK90(), .CLK180(), .CLK270(), .LOCKED(LOCKED_OUT), .PSDONE(), .STATUS()); defparam DCM_SP_INST.CLK_FEEDBACK = "NONE"; defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0; defparam DCM_SP_INST.CLKFX_DIVIDE = 25; defparam DCM_SP_INST.CLKFX_MULTIPLY = 4; defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; defparam DCM_SP_INST.CLKIN_PERIOD = 20.000; defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE"; defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW"; defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW"; defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE"; defparam DCM_SP_INST.FACTORY_JF = 16'hC080; defparam DCM_SP_INST.PHASE_SHIFT = 0; defparam DCM_SP_INST.STARTUP_WAIT = "FALSE"; endmodule