`ifdef EXECUTE `INSN_LD_reg_imm8: begin case (cycle) 0: begin `EXEC_INC_PC; `EXEC_NEXTADDR_PCINC; rd <= 1; end 1: begin `EXEC_INC_PC; if (opcode[5:3] == `INSN_reg_dHL) begin address <= {registers[`REG_H], registers[`REG_L]}; wdata <= rdata; rd <= 0; wr <= 1; end else begin `EXEC_NEWCYCLE; end end 2: begin `EXEC_NEWCYCLE; end endcase end `endif `ifdef WRITEBACK `INSN_LD_reg_imm8: case (cycle) 0: begin end 1: case (opcode[5:3]) `INSN_reg_A: begin registers[`REG_A] <= rdata; end `INSN_reg_B: begin registers[`REG_B] <= rdata; end `INSN_reg_C: begin registers[`REG_C] <= rdata; end `INSN_reg_D: begin registers[`REG_D] <= rdata; end `INSN_reg_E: begin registers[`REG_E] <= rdata; end `INSN_reg_H: begin registers[`REG_H] <= rdata; end `INSN_reg_L: begin registers[`REG_L] <= rdata; end `INSN_reg_dHL: begin /* Go off to cycle 2 */ end endcase 2: begin end endcase `endif