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[fpgaboy.git] / core / insn_ld_sp_hl.v
1 `define INSN_LD_SP_HL           9'b011111001
2
3 `ifdef EXECUTE
4         `INSN_LD_SP_HL: begin
5                 case (cycle)
6                 0:      tmp <= `_H;
7                 1:      begin
8                                 `EXEC_NEWCYCLE
9                                 `EXEC_INC_PC
10                                 tmp <= `_L;
11                         end
12                 endcase
13         end
14 `endif
15
16 `ifdef WRITEBACK
17         `INSN_LD_SP_HL: begin
18                 case (cycle)
19                 0:      `_SPH <= tmp;
20                 1:      `_SPL <= tmp;
21                 endcase
22         end
23 `endif
Partial Nintendo GameBoy / GBZ80 implementation on a Xilinx FPGA
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