[fpgaboy.git] / core / insn_ld_reg_imm16.v

`define INSN_LD_reg_imm16       9'b000xx0001

`ifdef EXECUTE
        `INSN_LD_reg_imm16: begin
                `EXEC_INC_PC
                case (cycle)
                0:      `EXEC_READ(`_PC + 1)
                1:      `EXEC_READ(`_PC + 1)
                2:      `EXEC_NEWCYCLE
                endcase
        end
`endif

`ifdef WRITEBACK
        `INSN_LD_reg_imm16: begin
                case (cycle)
                0:      begin /* */ end
                1:      begin
                                case (opcode[5:4])
                                `INSN_reg16_BC: `_C <= rdata;
                                `INSN_reg16_DE: `_E <= rdata;
                                `INSN_reg16_HL: `_L <= rdata;
                                `INSN_reg16_SP: `_SPL <= rdata;
                                endcase
                        end
                2:      begin
                                case (opcode[5:4])
                                `INSN_reg16_BC: `_B <= rdata;
                                `INSN_reg16_DE: `_D <= rdata;
                                `INSN_reg16_HL: `_H <= rdata;
                                `INSN_reg16_SP: `_SPH <= rdata;
                                endcase
                        end
                endcase
        end
`endif